ADM7154

• Edge compute platform for machine vision and real-time sensor fusion for autonomous robots and vehicles applications
• 8 x GMSL2 camera interfaces with up to 6 Gbps/channel
• 10 Gbps SFP+ Ethernet interface
• IEEE 1588 Precision Time Protocol for synchronization with host systems and other edge devices
• Advanced embedded processing capabilities
• ROS2 compliant
• Advanced camera triggering functions and control features
• Open-source software stack and FPGA design to enable custom applications development

The AD-GMSL2ETH-SL is an edge compute platform enabling low-latency data transfer from eight Gigabit Multimedia Serial Link™ (GMSL) interfaces on to a 10 Gb Ethernet link. The target applications include autonomous robots and vehicles where machine vision and real-time sensor fusion is critical.

The system includes two MAX96724 Quad Tunneling GMSL2/1 to CSI-2 Deserializers, enabling connectivity to eight GMSL cameras. The video data from the cameras is transferred from the MAX96724 deserializers via MIPI CSI2 interfaces to an AMD KV26 System on Module which implements the logic to aggregate the video data from all the GMSL cameras into a 10 Gb Ethernet link, so that it can be sent to a central processing unit.

The IEEE 1588 Precision Time Protocol (PTP) with hardware timestamping is supported, enabling accurate synchronization with host systems and other edge devices. The AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner is used to generate the required clocks for the 10 Gb Ethernet interface and the PTP logic.

A software networking stack can be used to realize the communication over the 10 Gb Ethernet link. Since the system runs Linux tools like gstreamer can be used to send the video data to a host and remote connection into the system is possible via ssh. The software network stack has limitations in terms of the maximum achievable transfer rate, and for this reason there is also the option to have an FPGA accelerated UDP or TCP implementation with Real Time Transfer (RTP) protocol for data packetization, which can get up to the maximum achievable data rate on the 10 Gb ethernet interface.

Accurate camera triggering control is achieved through dedicated FPGA logic, with configurable frequency and phase as well as selecting the trigger source between the internal logic and external signals.

Sixteen (16) general purpose I/O pins are available with software configurable functionality, operating at 3.3 V voltage level. A RS232 dedicated interface can be used to connect UART peripherals such as GNSS devices.

The design is accompanied by an open-source software stack and FPGA design, and reference applications, enabling custom software development to start from a proven implementation.

APPLICATIONS

• Autonomous robots and vehicles

• TX
  • 16-bit 12GSPS RFDAC
  • JESD204B Interface
    • 8 lanes up to 12.5Gbps
  • 1x/2x/4x/6x/8x/12x/16x/24x/32x Interpolation
  • 64-bit NCO at max rate
  • Analog Modes of Operation:
    • Normal Mode: 6GSPS DAC rate
      • Synthesis up to 2.5GHz (1st Nyquist)
    • Mix Mode: 6GSPS DAC rate
      • Synthesis in 2nd & 3rd Nyquist zones
    • 2X Normal Mode: 12GSPS DAC rate
      • Synthesis up to 6GHz (1st Nyquist)
    • Excellent dynamic performance
• RX
  • 3.2GHz full power bandwidth at 2.5GSPS
    • Noise Density = -149.5dBFs/Hz, ENOB = 9.5 bits
    • SFDR = 77 dBc at 1GHz Ain (2.5Gsps)
    • SFDR = 77dBc at 1.8GHz Ain (2.5Gsps)
  • +/-0.3 LSB DNL, +/-1.0 LSB INL
  • Dual supplies : 1.3V and 2.5V
  • 8 or 6 Lane JESD204B Outputs
  • Programmable clipping threshold for Fast Detect output
  • Two Integrated wide band digital down converters (DDC) per channel
    • 10-bit complex NCO
    • 2 cascaded half band filters (dec/8, dec/16)
  • Timestamp for synchronous processing alignment
    • SYSREF Setup/Hold detector
  • Programmable Interrupt (IRQ) event monitor

The AD-FMComms11-EBZ board is a system platform board for communication infrastructure applications that demonstrates the Direct to RF (DRF) transmitter and observation receiver architecture. Using high sample rate RFDAC(s) and RFADC(s), a number of components in previous generation transmitters can be eliminated, such as mixers, modulators, IF amplifiers and filters. The objective being to bring the ADC or DAC as close to the antenna as possible, leading to possibly more cost effective and efficient communications solution.

It is composed of multi-GSPS RF ADC and DAC, AD9625 and AD9162 respectively. The transmit path contains a balun, low pass filter, gain block and variable attenuation to produce an output appropriate for a power amplifier module. Along the observation path, the PA output is coupled back into the board through a variable attenuator, a balun and finally the ADC. Clock management is taken care of on board; all the necessary clocks are generated from a reference. Power management is present as well.

• Input voltage range: 2.3 V to 5.5 V
• Maximum output current: 600 mA
• Low noise
• 0.9 µV rms total integrated noise from 100 Hz to 100 kHz
• 1.6 µV rms total integrated noise from 10 Hz to 100 kHz
• Initial accuracy: ±0.5%
• Fixed 3.3 V (ADM7154) and adjustable (ADM7155) output versions
• 8-lead LFCSP and 8-lead SOIC packages

The ADM7154CP-3.3EVALZ, ADM7154CP-1.8EVALZ and ADM7155CP-02-EVALZ evaluation boards are used to demonstrate the functionality of the ADM7154 and ADM7155 linear regulators, respectively.

Simple device measurements, such as line and load regulation, dropout, and ground current, can be demonstrated with just a single voltage source, a voltmeter, an ammeter, and load resistors.

For more details about the linear regulators, refer to the ADM7154 and ADM7155 data sheets.

Evaluation Kit Contents

•     ADM7154CP-3.3EVALZ, ADM7154CP-1.8EVALZ or ADM7155CP-02-EVALZ evaluation board

Additional Equipment Needed

•     DC power supply
•     Multimeters for voltage and current measurements
•     Electronic or resistive loads

• Four channels of 1.0 GSPS conversion utilizing JESD204B high speed serial interface
• Driver amplifier interface with 21dB voltage gain adjustment
• Optional on-board or external clocking
• Specific design and I/O added for multi-board synchronization

The AD-FMCADC4-EBZ is a high speed 4-channel data acquisition board featuring two AD9680 dual channel ADC at 1000 MSPS and four ADA4961 low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 clock generator. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9680 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/anti-jamming measures.

The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1).

This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.

The design of the board is specifically tailored to synchronizing multiple AD-FMCADC4-EBZ boards together. For more information on synchronization please refer to A Test Method for Synchronizing Multiple GSPS Converters. The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring its internal registers via SPI.

AD-FREQCVT1-EBZは、AD9361を内蔵するFMCOMMS3/4/5ボードのアドオン・ボードです。完全なチップ・レベルの設計パッケージはADI製品ページにありますが、カード上の情報、カードの使用方法、周りのデザイン・パッケージ、動作に必要なソフトウェアは、アナログwikiサイトにあります。

AD-FREQCVT1-EBZの目的は、周波数の上下変換を行い、1MHzまで下げてAD9361が動作できるようにすることです。

AD-SYNCHRONA14-EBZは、周波数および位相が極めて正確に制御されたソース・クロックを必要とするアプリケーションの評価やプロトタイピングに使用するのに最適な、自己完結型のデバイスです。アナログ・デバイセズのAD9545およびHMC7044を中心に設計されており、複雑なシステムでのクロック分配とマルチチャンネル同期が大幅に簡素化できます。ただし、実験室環境で熟練した技術者が使用することを意図したものであり、商用の最終製品は目的としていません。全機能を完備したリファレンス設計として利用でき、エンド・カスタマのアプリケーションの必要性に応じてカスタマイズできます。設計の詳細は無料で入手できます。

AD-SYNCHRONA14-EBZは、1Uの物理的フォーム・ファクタで提供されます。必要なケーブルが既に大半の実験室に備わっており業界で一般的となっている、SMAコネクタとTwinAXインターフェースが用いられています。

内蔵のOCXOを用いることでスタンドアロン動作が可能です。あるいは、独立な3個の高速差動クロック入力、10MHzリファレンス、1個のPPS入力など、外部ソースの選択も可能です。この柔軟性と、内部VCXOの100MHzまたは122.88MHzのどちらかを選択できる機能を合わせることで、対象周波数と必要精度に関しほぼ限りない選択が可能となり、広範なアプリケーション分野に適用できます。

アプリケーション

• 高精度リファレンス・クロック分配
• 1つのソースでクロック供給を行うシステム
• 100MHzまたは122.88MHzから生成するクロック
• フェーズド・アレイ・システム、RADAR、EW、SATCOMS、SDR
• ベンチ機器
• リモート制御動作

The HMCAD1520-EBZ (HMCAD1511-EBZ) supports the HMCAD1520 (HMCAD1511), a 12bit (8bit), 640MSPS (1GSPS) multi-channel analog-to-digital converter. The board uses LTM8078 switching regulator and ADM7154 LDO as its power supply and uses LTC6419 as an optional high-speed ADC driver. The board is designed to interface directly with FPGA development boards with FMC (Vita57.1) connector.

This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the EVAL-SDP-CH1Z data capture card, allowing users to download captured data for analysis. The device control and subsequent data analyses can now be done using the ACE software package.

• DC～5.5GHzのシングル・トーン発生器
• 0dBm～-40dBmの範囲で+/-0.5dBの広帯域振幅キャリブレーション
• 48ビットの周波数チューニング分解能（～43uHz）
• 内蔵VCXOによる高速起動
• Raspberry Pi 3B+、4、Zero W、Zero 2Wと互換性あり