AD9279
RECOMMENDED FOR NEW DESIGNSOctal LNA/VGA/AAF/ADC and CW I/Q Demodulator
- Part Models
- 1
- 1ku List Price
- Starting From $74.47
Part Details
- Lowpower : 141 mW per channel, TGC mode, 40 MSPS;
60 mW per channel, CW mode - 10 mm × 10 mm, 144-ball CSP-BGA
- TGC channel input-referred noise: 0.8 nV/√Hz, max gain
- Flexible power-down modes
- Fast recovery from low power standby mode: <2us
- Overload recovery: <10 ns
- Input-referred noise: 0.75 nV/√Hz , gain = 21.3 dB
- Programmable gain: 15.6 dB/17.9 dB/21.3 dB
- 0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
- Dual-mode active input impedance matching
- Bandwidth (BW) > 100 MHz
- Attenuator range: −45 dB to 0 dB
- Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
- Linear-in-dB gain control
- Programmable second-order LPF from 8 MHz to 18 MHz
- Programmable HPF
- SNR: 70 dB, 12 bits up to 80 MSPS
- Serial LVDS (ANSI-644, Low power/reduced signal)
- Individual programmable phase rotation
- Output dynamic range per channel: >160 dBc/√Hz
- Output-referred SNR: 155 dBc/√Hz, 1kHz offset, -3dBFS
The AD9279 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC), and an I/Q demodulator with programmable phase rotation.
Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 52 dB. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB. In CW Doppler mode, each LNA output drives an I/Q demod-ulator that has independently programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface.
Documentation
Data Sheet 1
Technical Articles 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9279BBCZ | 144-Ball CSPBGA (10mm x 10mm x 1.4mm) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 0
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Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 5 | ||
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| ADCLK946 | RECOMMENDED FOR NEW DESIGNS | Six LVPECL Outputs, SiGe Clock Fanout Buffer |
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Low Noise Op Amps (≤ 10nV/√Hz) 2 | ||
| ADA4896-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers |
| ADA4897-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power Operational Amplifier |
| Single Channel A/D Converters 1 | ||
| AD7982 | PRODUCTION | 18-Bit, 1 MSPS PulSAR ADC in MSOP/LFCSP |
| Single-Ended to Differential Amplifiers 2 | ||
| AD8138 | PRODUCTION | Low Distortion Differential ADC Driver |
| ADA4932-1 | RECOMMENDED FOR NEW DESIGNS | Low Power Differential ADC Driver |
Tools & Simulations
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolEvaluation Kits
FPGA-Based Data Capture Kit
Resources
Software
AD9279 Evaluation Board