ADCLK846
RECOMMENDED FOR NEW DESIGNS1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer
- Part Models
- 2
- 1ku List Price
- Starting From $5.14
Part Details
- Selectable LVDS/CMOS outputs
- Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs
- <16 mW per channel (100 MHz operation)
- 54 fs integrated jitter (12 kHz to 20 MHz)
- 100 fs additive broadband jitter
- 2.0 ns propagation delay (LVDS)
- 135 ps output rise/fall (LVDS)
- 65 ps output-to-output skew (LVDS)
- Sleep mode
- Pin-programmable control
- 1.8 V power supply
The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs.
The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.
Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device.
This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Low jitter clock distribution
- Clock and data signal restoration
- Level translation
- Wireless communications
- Wired communications
- Medical and industrial imaging
- ATE and high performance instrumentation
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Technical Articles 3
Frequently Asked Question 1
Circuit Note 1
Tutorial 1
Product Selection Guide 1
Webcast 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADCLK846BCPZ | 24-Lead LFCSP (4mm x 5mm w/ EP) | ||
| ADCLK846BCPZ-REEL7 | 24-Lead LFCSP (4mm x 5mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Feb 1, 2024 - 24_0009 Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process |
||
| ADCLK846BCPZ | PRODUCTION | |
| ADCLK846BCPZ-REEL7 | PRODUCTION | |
|
May 5, 2014 - 14_0020 Conversion of 4x4mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines. |
||
| ADCLK846BCPZ | PRODUCTION | |
| ADCLK846BCPZ-REEL7 | PRODUCTION | |
|
May 22, 2012 - 12_0063 Conversion of Select Sizes of LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE-Korea. |
||
| ADCLK846BCPZ | PRODUCTION | |
| ADCLK846BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Tools & Simulations
IBIS Model 1
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Open ToolEvaluation Kits
ADCLK846 Evaluation Board