CN0348

Figure 1 shows the single supply signal chain that consists of a voltage reference, a digital-to-analog converter (DAC) and a DAC buffer. The reference voltage of the DAC is equal to the supply voltage, V_DD, to maximize dynamic output range and signal-to-noise ratio. With this configuration, a rail-to-rail input and output buffer amplifier is required.

The DAC is the AD5541A 16-bit, serial input, voltage output segmented R/2R CMOS DAC. The output voltage of the DAC is dependent on the reference voltage, as shown in the following equation:

This gives a V_OUT of 2.5 V at mid-scale, and 5 V at full-scale.

The LSB size is 5 V/65,536 = 76.3 µV

One LSB at 16 bits is also 0.0015% of full-scale or 15 ppm FS.

The ADR4550 voltage reference provides a high precision, low noise (2.8 µV p-p, 0.1 Hz to 10 Hz) and stable reference to the DAC. The ADR4550 uses an innovative core topology to achieve high accuracy while offering industry-leading temperature stability and noise performance. The low output voltage temperature coefficient (2 ppm/°C maximum) and low long-term output voltage drift of the device also improve system accuracy over time and temperature variations.

The initial room temperature accuracy of the ADR4550B is ±0.02% maximum, which is approximately 14 LSBs at 16 bits. This initial error can be removed with a system calibration. The voltage reference drives the REF pin of the DAC as well as provides power to the DAC and the output buffer. As a result, it must supply up to 3.9 mA of load current. The ADR4550 can drive up to 10 mA with 25 ppm/mA load current regulation.

The ADR4550 reference should be placed as close to the REF pin of the DAC as possible to minimize the length of the output traces, and therefore, the error introduced by the voltage drop. Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this voltage drop can be several millivolts or more, introducing a considerable error. A 1 inch long, 0.005 inch wide trace of 1oz copper has a resistance of approximately 100 mΩ at room temperature. With a load current of 10 mA, this can introduce a 1 mV error.

The ADA4500-2 is selected as the output buffer. This device is a high precision amplifier with maximum offset voltage of 120 μV, offset drift of less than 5.5 μV/°C, 0.1 Hz to 10 Hz noise of 2 μV p-p, and maximum input bias current of 2 pA. Its key feature of rail-to-rail input and output swing with zero crossover distortion makes it a suitable candidate as a DAC buffer.

A typical rail-to-rail input amplifier uses two differential pairs to achieve rail-to-rail input swing (see Tutorial MT-035). One differential pair is active at the higher range of the input common-mode voltage, and the other pair is active at the lower end. This classic dual differential pair topology introduces crossover distortion during the handoff of one differential pair to the other. The change in offset voltage causes nonlinearity when the amplifier is used as a DAC buffer. The ADA4500-2 uses an integrated charge pump in its input structure to achieve rail-to-rail input swing without the need for a second differential pair. Therefore, it does not exhibit crossover distortion. Using a zero crossover distortion amplifier in this single supply system provides wide dynamic output range while maintaining linearity over the input common mode/input digital code range. Details of the operation of the ADA4500-2 can be found on the ADA4500-2 data sheet.

The output impedance of the DAC is constant (typically 6.25 kΩ) and code-independent. However, the output buffer should have a high input impedance (low input bias current) to minimize errors. The ADA4500-2 is a suitable candidate with high input impedance and 2 pA maximum of input bias current at room temperature, and 190 pA maximum of input bias current over temperature. This results in 1.2 μV of worst-case error due to input bias current, which is much less than 1 LSB.

The AD5541A is available 10-lead MSOP or 10-lead LFCSP. The ADR4550 is available in 8-lead SOIC, and the ADA4500-2 is available in 8-lead MSOP or 8-lead LFCSP.

Measured results show that the combination of the AD5541A, ADR4550 and ADA4500-2 is an excellent solution for high accuracy, low noise performance applications. The ADA4500-2 maintains the linearity of the DAC with no crossover distortion.

Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) Measurements

INL error is the deviation in LSB of the actual DAC transfer function from an idealized transfer function. DNL error is the difference between an actual step size and the ideal value of 1 LSB. This system solution provides a 16-bit resolution with ±1 LSB DNL and INL. Figure 2 and Figure 3 show the DNL and INL performance of the circuit.

Note that the DNL and INL measurements exclude the 200 codes (approximately 15 mV) from either end of the range. This is because the rail-to-rail output stage becomes nonlinear over this region as described in Tutorial MT-035.

Figure 4 shows the nonlinearity introduced by using an op amp with a traditional rail-to-rail input stage. Note that the peak error of about 4 LSBs occurs when the common-mode voltage is about 1.7 V away from the +5 V supply rail.

Board Layout Considerations

It is important to carefully consider the power supply and ground return layout on the board. The printed circuit board should have separate analog and digital sections. If the circuit is used in a system where multiple devices require an analog ground to digital ground connection, make the connection at only one point. Power supplies to all components should be bypassed with at least 0.1uF capacitors. These bypass capacitors should be as physically close as possible to the device, with the capacitor ideally right up against the device. The 0.1uF capacitor should be chosen to have low effective series resistance (ESR) and low effective series inductance (ESL), such as ceramic capacitors. This 0.1μF capacitor provides a low impedance path to ground for transient currents. The power supply line should also have as large a trace as possible to provide a low impedance supply path. Proper layout, grounding, and decoupling techniques should be used to achieve optimum performance (see Tutorial MT-031, Grounding Data Converters and Solving the Mystery of AGND and DGND and Tutorial MT-101, Decoupling Techniques).