AD9649
PRODUCTION14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
- Part Models
- 8
- 1ku List Price
- Starting From $15.87
Part Details
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input - SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input - Low power
45 mW at 20 MSPS
87 mW at 80 MSPS
- Differential input with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- 2 V p-p differential analog input
- DNL = ±0.35 LSB
- Serial port control options
Offset binary, gray code, or twos complement data format - See data sheet for additional features
The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip volt-age reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.
The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.
The AD9649 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
- The AD9649 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
- The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
- A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes.
- The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9629 12-bit ADC and the AD9609 10-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA - Smart antenna systems
- Battery-powered instruments
- Handheld scope meters
- Portable medical imaging
- Ultrasound
- Radar/LIDAR
Documentation
Data Sheet 1
User Guide 1
Application Note 8
Technical Articles 2
Evaluation Design File 2
Device Drivers 2
Webcast 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9649BCPZ-20 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZ-40 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZ-65 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZ-80 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZRL7-20 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZRL7-40 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZRL7-65 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) | ||
| AD9649BCPZRL7-80 | 32-Lead LFCSP (5mm x 5mm x 0.85mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Feb 1, 2024 - 24_0009 Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process |
||
| AD9649BCPZ-20 | PRODUCTION | |
| AD9649BCPZ-40 | PRODUCTION | |
| AD9649BCPZ-65 | PRODUCTION | |
| AD9649BCPZ-80 | PRODUCTION | |
| AD9649BCPZRL7-20 | PRODUCTION | |
| AD9649BCPZRL7-40 | PRODUCTION | |
| AD9649BCPZRL7-65 | PRODUCTION | |
| AD9649BCPZRL7-80 | PRODUCTION | |
|
Mar 13, 2017 - 17_0035 Power Down Sequence and DRVDD Voltage Restriction for AD9649, AD9629 and AD9609. |
||
| AD9649BCPZ-20 | PRODUCTION | |
| AD9649BCPZ-40 | PRODUCTION | |
| AD9649BCPZ-65 | PRODUCTION | |
| AD9649BCPZ-80 | PRODUCTION | |
| AD9649BCPZRL7-20 | PRODUCTION | |
| AD9649BCPZRL7-40 | PRODUCTION | |
| AD9649BCPZRL7-65 | PRODUCTION | |
| AD9649BCPZRL7-80 | PRODUCTION | |
|
Nov 10, 2014 - 14_0047 Conversion of 5x5mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines. |
||
| AD9649BCPZ-20 | PRODUCTION | |
| AD9649BCPZ-40 | PRODUCTION | |
| AD9649BCPZ-65 | PRODUCTION | |
| AD9649BCPZ-80 | PRODUCTION | |
| AD9649BCPZRL7-20 | PRODUCTION | |
| AD9649BCPZRL7-40 | PRODUCTION | |
| AD9649BCPZRL7-65 | PRODUCTION | |
| AD9649BCPZRL7-80 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 2
Evaluation Software 0
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Digital Control VGAs 2 | ||
| AD8375 | PRODUCTION | Ultralow Distortion IF VGA |
| AD8370 | PRODUCTION | 750 MHz Digitally Controlled Variable Gain Amplifier |
| Fully Differential Amplifiers 2 | ||
| ADL5561 | RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4937-1 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Single) |
| ADA4938-1 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Single) |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolS-Parameter 1
AD9649 IBIS Models 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolAD9649 Simulink ADIsimADC Model
Open ToolEvaluation Kits
FPGA-Based Data Capture Kit
Resources
Software
AD9649 Evaluation Board