AD9671
RECOMMENDED FOR NEW DESIGNSOctal Ultrasound AFE with Digital Demodulator, JESD204B
- Part Models
- 1
- 1ku List Price
- Starting From $96.30
Part Details
- 8 channels of LNA, VGA, AAF, ADC, and digital demodulator/decimator
- Low power: 150 mW per channel, time gain compensation (TGC) mode, 40 MSPS
62.5 mW per channel, continuous wave (CW) mode; <30 mW in power-down mode - 10 mm × 10 mm, 144-ball CSP_BGA
- TGC channel input referred noise: 0.82 nV/√Hz, maximum gain
- Flexible power-down modes
- Fast recovery from low power standby mode: <2 μs
- Low noise preamplifier (LNA)
- Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
- Programmable gain: 15.6 dB/17.9 dB/21.6 dB
- 0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
- Flexible active input impedance matching
- Variable gain amplifier (VGA)
- Attenuator range: 45 dB, linear-in-dB gain control
- Postamplifier (PGA) gain: 21 dB/24 dB/27 dB/30 dB
- See data sheet for additional features
The AD9671 is designed for low cost, low power, small size, and ease of use for medical ultrasound applications. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an AAF, an ADC, and a digital demodulator and decimator for data processing and bandwidth reduction.
Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended to differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user defined test patterns entered via the SPI.
Applications
- Medical imaging/ultrasound
- Nondestructive testing (NDT)
Documentation
Data Sheet 1
User Guide 1
Technical Articles 3
Informational 1
FPGA Interoperability Reports 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9671KBCZ | 144-Ball CSPBGA (10mm x 10mm x 1.4mm) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Mar 23, 2015 - 15_0033 AD9671/AD9675 Die Revision |
||
| AD9671KBCZ | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 0
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Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 5 | ||
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| ADCLK946 | RECOMMENDED FOR NEW DESIGNS | Six LVPECL Outputs, SiGe Clock Fanout Buffer |
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Low Noise Op Amps (≤ 10nV/√Hz) 2 | ||
| ADA4896-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers |
| ADA4897-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power Operational Amplifier |
| Single Channel A/D Converters 1 | ||
| AD7982 | PRODUCTION | 18-Bit, 1 MSPS PulSAR ADC in MSOP/LFCSP |
| Single-Ended to Differential Amplifiers 2 | ||
| AD8138 | PRODUCTION | Low Distortion Differential ADC Driver |
| ADA4932-1 | RECOMMENDED FOR NEW DESIGNS | Low Power Differential ADC Driver |
Tools & Simulations
AD9671 AMI Model
Open ToolEvaluation Kits
AD9671 Evaluation Board