ADF4383

The ADF4383 is a high performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of −239 dBc/Hz, low 1/f noise and high PFD frequency of 625 MHz in integer mode that can achieve ultra-low in-band noise and integrated jitter. The ADF4383 can generate frequencies in a fundamental octave range of 10 GHz to 20 GHz, thereby eliminating the need for subharmonic filters. The output dividers on the ADF4383 allows a complete output frequency range to be generated from 625 MHz to 20 GHz.

For multiple data converter clock applications, the ADF4383 automatically aligns its output to the input reference edge by including the output divider in the PLL feedback loop. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with <1 ps resolution is provided. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip alignment.

The simplicity of the ADF4383 block diagram eases development time with a simplified serial peripheral interface (SPI) register map, external SYNC input, and repeatable multichip alignment in both integer and fractional mode.

APPLICATIONS

• High performance data converter clocking
• Wireless infrastructure (MC-GSM, 5G, 6G)
• Test and measurement