AD9644
RECOMMENDED FOR NEW DESIGNS14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
- Part Models
- 6
- 1ku List Price
- Starting From $40.13
Part Details
- JESD204A coded serial digital outputs
- SNR = 73.7 dBFS at 70 MHz and 80 MSPS
- SNR = 71.7 dBFS at 70 MHz and 155 MSPS
- SFDR = 92 dBc at 70 MHz and 80 MSPS
- SFDR = 92 dBc at 70 MHz and 155 MSPS
- Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS
- 1.8 V supply operation
- IF sampling frequencies to 250 MHz
- Integer 1-to-8 input clock divider
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS - -150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS
- Please see data sheet for additional features
The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.
The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
Applications- Communications
- Diversity radio systems
- Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
- Ultrasound equipment
- An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock.
- The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs.
- Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.
Documentation
Data Sheet 1
User Guide 1
Application Note 8
Technical Articles 3
Informational 1
Video 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9644BCPZ-155 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9644BCPZ-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9644BCPZRL7-155 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9644BCPZRL7-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9644CCPZ-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) | ||
| AD9644CCPZRL7-80 | 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
| AD9644BCPZ-155 | PRODUCTION | |
| AD9644BCPZ-80 | PRODUCTION | |
| AD9644BCPZRL7-155 | PRODUCTION | |
| AD9644BCPZRL7-80 | PRODUCTION | |
| AD9644CCPZ-80 | PRODUCTION | |
| AD9644CCPZRL7-80 | PRODUCTION | |
|
Sep 13, 2017 - 16_0077 CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea. |
||
| AD9644BCPZ-155 | PRODUCTION | |
| AD9644BCPZ-80 | PRODUCTION | |
| AD9644BCPZRL7-155 | PRODUCTION | |
| AD9644BCPZRL7-80 | PRODUCTION | |
| AD9644CCPZ-80 | PRODUCTION | |
| AD9644CCPZRL7-80 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Digital Control VGAs 2 | ||
| AD8376 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion IF Dual VGA |
| AD8372 | RECOMMENDED FOR NEW DESIGNS | 41 dB Range, 1 dB Step Size, Programmable Dual VGA |
| Fully Differential Amplifiers 2 | ||
| ADL5561 | RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4937-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolS-Parameter 2
IBIS Model 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolAD9644 Simulink ADIsimADC Model
Open ToolEvaluation Kits
AD9644 Evaluation Board