AD9484
RECOMMENDED FOR NEW DESIGNS8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter
- Part Models
- 2
- 1ku List Price
- Starting From $46.22
Part Details
- SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
- ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
- SFDR = 79 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
- Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.1 LSB typical
- Integrated input buffer
- LVDS at 500 MSPS (ANSI-644 levels)
- 1 GHz full power analog bandwidth
- On-chip reference, no external decoupling required
- Low power dissipation
670 mW at 500 MSPS—LVDS SDR output - See datasheet for additional features
The AD9484 is an 8-bit, monolithic, sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port).
The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.
Fabricated on an advanced BiCMOS process, the AD9484 is available in a 56-lead LFCSP, and is specified over the industrial temperature range (−40°C to +85°C). This product is protected under U.S. and international patents.
PRODUCT HIGHLIGHTS
- High Performance.
Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input. - Ease of Use.
LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. - Serial Port Control.
Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power down, gain adjust, and output test pattern generation.
APPLICATIONS
- Wireless and wired broadband communications
- Cable reverse path
- Communications test equipment
- Low cost digital oscilloscopes
- Satellite subsystems
- Power amplifier linearization
Documentation
Data Sheet 1
User Guide 1
Application Note 11
Technical Articles 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9484BCPZ-500 | 56-Lead LFCSP (8mm x 8mm w/ EP) | ||
| AD9484BCPZRL7-500 | 56-Lead LFCSP (8mm x 8mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
| AD9484BCPZ-500 | PRODUCTION | |
| AD9484BCPZRL7-500 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 5 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9523 | NOT RECOMMENDED FOR NEW DESIGNS | 14-Output, Low Jitter Clock generator |
| AD9524 | NOT RECOMMENDED FOR NEW DESIGNS | 6 Output, Dual Loop Clock Generator |
| Digital Control VGAs 3 | ||
| ADL5201 | Obsolete | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| ADL5202 | Obsolete | Wide Dynamic Range, High Speed, Digitally Controlled VGA |
| ADL5240 | LAST TIME BUY | 100 MHz TO 4000 MHz RF/IF Digitally Controlled VGA |
| Fully Differential Amplifiers 1 | ||
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 1 | ||
| ADA4927-1 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Current Feedback Differential ADC Driver |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolAD9434/AD9484 IBIS Model 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolAD9484 Simulink ADIsimADC Model
Open ToolEvaluation Kits
AD9484 Evaluation Board
Resources
FPGA-Based Data Capture Kit