AD9269
RECOMMENDED FOR NEW DESIGNS16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
- Part Models
- 7
- 1ku List Price
- Starting From $62.92
Part Details
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- Integrated quadrature error correction (QEC)
- SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input - SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input - Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
- Differential input with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- 2V p-p differential analog input
- DNL = −0.5/+1.1 LSB
- Serial port control options
- Offset binary, gray code, or twos complement data format
- Optional clock duty cycle stabilizer (DCS)
- See data sheet for additional features
The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- Battery-powered instruments
- Hand held scope meters
- Portable medical imaging
- Ultrasound
- Radar/LIDAR
Documentation
Data Sheet 1
User Guide 2
Application Note 9
Technical Articles 3
Evaluation Design File 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9269BCPZ-20 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZ-40 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZ-65 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZRL7-20 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZRL7-40 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZRL7-65 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9269BCPZRL7-80 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
| AD9269BCPZ-20 | PRODUCTION | |
| AD9269BCPZ-40 | PRODUCTION | |
| AD9269BCPZ-65 | PRODUCTION | |
| AD9269BCPZRL7-20 | PRODUCTION | |
| AD9269BCPZRL7-40 | PRODUCTION | |
| AD9269BCPZRL7-65 | PRODUCTION | |
| AD9269BCPZRL7-80 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Baseband Programmable VGA-Filters 1 | ||
| ADRF6516 | Obsolete | 31 MHz, Dual Programmable Filters and Variable Gain Amplifiers |
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Digital Control VGAs 2 | ||
| AD8372 | RECOMMENDED FOR NEW DESIGNS | 41 dB Range, 1 dB Step Size, Programmable Dual VGA |
| AD8376 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion IF Dual VGA |
| Fully Differential Amplifiers 2 | ||
| ADL5561 | RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4937-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolAD9269 IBIS Model 1
SPICE Model 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolAD9269 Simulink ADIsimADC Model
Open ToolEvaluation Kits
FPGA-Based Data Capture Kit
Resources
Software
AD9269 Evaluation Board