AD9204
PRODUCTION10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
- Part Models
- 8
- 1ku List Price
- Starting From $6.61
Part Details
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- SNR
- 61.3 dBFS at 9.7 MHz input
- 61.0 dBFS at 200 MHz input
- SFDR
- 75 dBc at 9.7 MHz input
- 73 dBc at 200 MHz input
- Low power
- 30 mW per channel at 20 MSPS
- 63 mW per channel at 80 MSPS
- Differential input with 700 MHz bandwidth
- On-chip voltage reference and sample-and-hold circuit
- DNL = ±0.11 LSB
- Serial port control options
- Scalable analog input: 1 V p-p to 2 V p-p differential
- Offset binary, gray code, or twos complement data format
- Optional clock duty cycle stabilizer
- Integer 1-to-8 input clock divider
- Built-in selectable digital test pattern generation
- Energy-saving power-down modes
- Data clock out with programmable clock and data alignment
The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.
The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
- The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
- The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
- A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes.
- The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9251 and AD9258 14-bit ADCs, and the AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers
- GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
- I/Q demodulation systems
- Smart antenna systems
- Battery-powered instruments
- Handheld scope meters
- Ultrasound
- Radar/LIDAR
- PET/SPECT imaging
Documentation
Data Sheet 1
User Guide 2
Application Note 9
Technical Articles 2
Evaluation Design File 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9204BCPZ-20 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZ-40 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZ-65 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZ-80 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZRL7-20 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZRL7-40 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZRL7-65 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9204BCPZRL7-80 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
| AD9204BCPZ-20 | PRODUCTION | |
| AD9204BCPZ-40 | PRODUCTION | |
| AD9204BCPZ-65 | PRODUCTION | |
| AD9204BCPZ-80 | PRODUCTION | |
| AD9204BCPZRL7-20 | PRODUCTION | |
| AD9204BCPZRL7-40 | PRODUCTION | |
| AD9204BCPZRL7-65 | PRODUCTION | |
| AD9204BCPZRL7-80 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Digital Control VGAs 2 | ||
| AD8372 | RECOMMENDED FOR NEW DESIGNS | 41 dB Range, 1 dB Step Size, Programmable Dual VGA |
| AD8376 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion IF Dual VGA |
| Fully Differential Amplifiers 2 | ||
| ADL5561 | RECOMMENDED FOR NEW DESIGNS |
2.9 GHz Ultralow Distortion RF/IF Differential Amplifier |
| ADL5562 | RECOMMENDED FOR NEW DESIGNS | 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4937-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
Tools & Simulations
AD9204 IBIS Models 1
Visual Analog
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
Open ToolS-Parameter 1
Evaluation Kits
FPGA-Based Data Capture Kit
Resources
Software
AD9204 Evaluation Board