AD9988

RECOMMENDED FOR NEW DESIGNS

4T4R Direct RF Receiver and Transmitter

Data Sheet (Rev. A) Product Selection Table
Part Models
2
1ku List Price
Starting From $1200.54
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Part Details

  • Flexible, reconfigurable radio common platform design
    • Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R)
    • RF DAC/RF ADC RF frequency range up to 7.5 GHz
    • On-chip PLL with multichip synchronization
      • External RF clock input option
  • Versatile digital features
    • Selectable interpolation and decimation filters
    • Configurable DDCs and DUCs
      • 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC)
      • 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC)
      • FDUCs and FDDCs are fully bypassable
      • 2 independent 48-bit NCOs per DUC or DDC
    • Programmable 192-tap PFIR filter for receive equalization
      • Supports 4 different profile settings loaded via GPIO
    • Receive AGC support
      • Fast detect with low latency for fast AGC control
      • Signal monitor for slow AGC control
      • Dedicated AGC support pins
      • Transmit DPD support
        • Programmable delay and gain per transmit data path
        • Coarse DDC delay adjust for DPD observation path
      • Supports real or complex digital data (8-, 12-, or 16-bit)
  • Auxiliary features
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • Programmable GPIO pins support toggling between modes
    • TDD power savings option and sharing ADCs
  • SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps
    • 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx)
    • Supports Subclass 1
  • Supports multidevice synchronization
  • 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
AD9988
4T4R Direct RF Receiver and Transmitter
AD9988 Functional Block Diagram AD9988 Pin Configuration
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Documentation

Data Sheet 1

User Guide 2

Application Note 1

Technical Articles 2

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Software Resources

Device Drivers 2

  • AD908x GitHub Linux Driver Source Code

    • API Device Drivers 1

    Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.

    To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.

Hardware Ecosystem

Parts Product Life Cycle Description
µModule Buck Regulators 1
LTM8053
RECOMMENDED FOR NEW DESIGNS 40VIN, 3.5A/6A Step-Down Silent Switcher μModule Regulator
Clock Distribution Devices 3
HMC7043
RECOMMENDED FOR NEW DESIGNS

High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C
LTC6953
LAST TIME BUY Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support
LTC6955
LAST TIME BUY Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family
Clock Generation Devices 2
LTC6952
LAST TIME BUY Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support
HMC7044
RECOMMENDED FOR NEW DESIGNS High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support
Digital Control VGAs 2
ADL6316
RECOMMENDED FOR NEW DESIGNS 500 MHz to 1000 MHz Transmit VGA for Use with RF DACs and Transceivers
ADL6317
RECOMMENDED FOR NEW DESIGNS Transmit VGA for Use with RF DACs and Transceivers
Fully Differential Amplifiers 2
ADL5569
RECOMMENDED FOR NEW DESIGNS 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier
ADL5580
RECOMMENDED FOR NEW DESIGNS Fully Differential, 10 GHz ADC Driver with 10 dB Gain
Multiple Output Buck Regulators 3
LTM4633
RECOMMENDED FOR NEW DESIGNS Triple 10A Step-Down DC/DC μModule (Power Module) Regulator
LTM4644
LTM4644-1
Quad DC/DC μModule (Power Module) Regulator with Configurable 4A Output Array
LTM4616
RECOMMENDED FOR NEW DESIGNS Dual 8A per Channel Low VIN DC/DC μModule (Power Module) Regulator
Phase Locked Loop with Integrated VCO 1
ADF4377
RECOMMENDED FOR NEW DESIGNS Microwave Wideband Synthesizer with Integrated VCO
Positive Linear Regulators (LDO) 4
ADP1765
RECOMMENDED FOR NEW DESIGNS 5 A, Low VIN, Low Noise, CMOS Linear Regulator
ADP7158
RECOMMENDED FOR NEW DESIGNS 2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator
ADM7172
RECOMMENDED FOR NEW DESIGNS 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO
ADM7150
RECOMMENDED FOR NEW DESIGNS 800 mA, Ultra Low Noise/High PSRR LDO
Ultralow Noise Regulators 1
LTM8063
RECOMMENDED FOR NEW DESIGNS 40VIN, 2A Silent Switcher µModule Regulator
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Tools & Simulations

MxFE JESD204 Mode Selector Tool

The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.

Open Tool

ADC Companion Transport Layer RTL Code Generator Tool

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Open Tool

DAC Companion Transport Layer RTL Code Generator

These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Open Tool

ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

Open Tool

S-Parameter 2

IBIS Model 1

AD9081/AD9082/AD9986/AD9988 AMI Model

Open Tool

Thermal Models 1

High Speed Converter Toolbox for MATLAB

Open Tool
LTspice

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

Evaluation Kits

eval board
schematic 1
schematic 2
schematic 3
ADS9-V2EBZ

ADS9-V2EBZ Evaluation Board

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Features and Benefits

Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.

  • One (1) FMC+ connector.
  • Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
  • HMC DRAM
  • Simple USB 3.0 port interface.
  • Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE™ evaluation boards.

Product Details

When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.

eval board
schematic 4
schematic 5
schematic 6
schematic 7
EVAL-AD9988

Evaluating the AD9988 Mixed Signal, Front-End RF Transceiver

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Features and Benefits

  • Fully functional evaluation boards for the AD9988
  • PC software for control with analysis, control, evaluate (ACE) software On-board clocking provided by the HMC7044 manages device and FPGA clocking
  • Option to switch to external direct clocking

Product Details

The user guide describes the AD9081-FMCA-EBZ, AD9082-FMCA-EBZ, AD9986-FMCB-EBZ, and AD9988-FMCB-EBZ evaluation boards, which provide all of the support circuitry required to operate the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 in their various modes and configurations. The application software used to interface with the devices is also described. These evaluation boards connect to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software.

These evaluation boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx® or Intel®. Information on how to use these platforms to evaluate the AD9081 or the AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the MxFE® in various modes and to capture analog-to-digital converter

(ADC) data for analysis. The DPGDownloaderLite software (included in ACE installation) generates and transmits vectors to the digital-to-analog converters (DACs), which can then be sent to a spectrum analyzer for further analysis.

For additional information, see the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 data sheets and the UG-1578, the device user guide, which must be consulted in conjunction with the user guide when using the evaluation boards.
ADS9-V2EBZ
ADS9-V2EBZ Evaluation Board
ADS9-V2EBZANGLE-web ADS9-V2EBZBOTTOM-web ADS9-V2EBZTOP-web
EVAL-AD9988
Evaluating the AD9988 Mixed Signal, Front-End RF Transceiver
AD9986/AD9988 Evaluation Board AD998x Evaluation Board - Angle View AD998x Evaluation Board - Top View AD998x Evaluation Board - Bottom View

Latest Discussions

39 Weeks Ago
RE: Carrier aggregation through AD9988
39 Weeks Ago
RE: How can I send an external trigger by using ACE on ADS9+AD9988 platform?
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