CN0364

The data conversion is performed by the AD7173-8 24-bit, Σ-Δ analog-to-digital converter (ADC). The AD7173-8 is software configurable and allows 8 fully differential or 16 single-ended input channels, offering great flexibility via an internal crosspoint multiplexer. The AD7173-8 is in a small 6 mm × 6 mm LFCSP package, making it ideal where space is a premium. The internal clock and precision 2.5 V voltage reference minimize external components and result in additional space savings. The four programmable general-purpose output pins (GPIO0, GPIO1, GPO2, GPO3) allow external multiplexer control, which allows the control of the multiplexed HART interface and eliminates the need for additional control lines from the processor/controller. The AD7173-8 has internal calibration registers that can be programmed to provide offset and gain corrections for the full input path.

The AD5700-1 is the industry’s lowest power and smallest footprint HART-compliant modem and is used in conjunction with the current input channels to form a HART-compatible, 4 mA to 20 mA receiver solution. The AD5700-1 includes a precision internal oscillator that provides additional space savings, especially in isolated applications.

The ADG704 multiplexer provides HART connectivity to the multiple current input channels.

The ADuM5211 isolates two data channels (Tx, Rx) and also provides the 5 V power isolation via integrated isoPower^® technology. The ADuM3151 SPIsolator provides serial peripheral interface (SPI) isolation at clock rates of up to 17 MHz (B grade), as well as isolating three additional data channels.

The ADP2441 36 V, step-down, dc-to-dc regulator accepts an industrial standard 24 V supply, with wide tolerance on the input voltage. The ADP2441 steps the input voltage down to 5 V to power all controller side circuitry. The circuit also includes standard external protection on the 24 V supply terminals.

Voltage Input Circuit

Figure 2 shows the voltage input network for Channel 1.

The circuit has differential inputs and supports an input range of up to ±10 V with up to ±5 V common-mode voltage. The input impedance is ~900 kΩ, and the high values of R1 and R2 also protect the input during any high voltage transient events.

The R1, R2, R3, and R4 resistors form a differential resistor divider. The matching of these resistors is critical to the dc accuracy of the circuit. Single point calibration is recommended to remove the initial errors. Multipoint calibration can be used to cancel temperature drift effects. The board is populated by default with 0.1%, 25 ppm/°C resistors for R1, R2, R3, and R4.

The R5 and R6 resistors set the common-mode voltage for the ADC. The AD7173-8 has an allowable input voltage range of 0 V to 3.9 V. The bias voltage of +2.2 V, along with the input divider resistors, level shifts and attenuates the ±10 V input signal to ±1.1 V centered on a common-mode voltage of +2 V at the ADC input.

Input common-mode noise filtering is provided by R1||R3/C1 and R2||R4/C2, and is approximately 200 kHz. Differential noise filtering is provided by R1||R3, R2||R4, and C3, and is approximately 20 kHz.

Table 1 summarizes the parameters of the four voltage input channels. 

Current Input Circuit

Figure 3 shows the current input network for Channel 1.

The circuit has four current input channels, supporting a maximum input range of 0 mA to 24 mA. The input impedance of the circuit is 250 Ω, and the input is referenced to ground. A precision 100 Ω current sense resistor is used so that a 24 mA input produces 2.4 V, which is within the 2.5 V full-scale range of the AD7173-8 (using the internal 2.5 V voltage reference). The board is populated by default with a 0.1%, 10 ppm/°C R_SENSE resistor.

There are two input paths to separate ADC inputs. The fast input path is for channels not using HART, and the slow input path is for channels using HART.

The fast input path allows signals up to the full input bandwidth of the Σ-Δ ADC. It is also possible to use the internal sinc filters to reject the 1.2 kHz and 2.2 kHz HART frequencies. However, using the sinc filters requires running the relevant channel at the 400 SPS data rate (sinc3 filter), which increases the time required to convert all four channels.

The slow input contains a 16 Hz double-pole filter, which filters out the 1.2 kHz and 2.2 kHz HART digital signaling frequencies. Using this input, the Σ-Δ ADC can still run at its fast data rate and also reject the HART digital signaling frequencies. The time required to convert all four channels is not reduced. Operating the ADC at its fast data rate is especially useful if not all channels have HART enabled.

Table 2 summarizes the current input circuit parameters.

HART Input and Output Circuit

Figure 4 shows the HART input and output circuit.

The HART functionality is multiplexed between the four current input channels. The HART input and output networks are shared between the four channels using the two ADG704 multiplexers (SW1 and SW2 in Figure 4).

The HART input circuitry consists of a HART band-pass filter formed by R3, C1, C2, R4, and R5. This filter is described in the AD5700-1 data sheet. A switch (SW1) is used in each channel to switch the HART input circuitry to the active HART channel. The 150 kΩ resistor (R3) is present on each channel and is part of the HART band-pass filter, but also provides additional protection for the switch (SW1). The HART input connects directly to the current input terminal to ensure that the correct voltage levels are received at the ADC_IP pin of the AD5700-1.

A switch (SW2) is used in each channel to switch the HART output circuitry to the active HART channel. Capacitor C3 couples the HART signal. The combination of R1, C3, R6, and R7 was carefully chosen to ensure that the voltage of the HART_OUT pin of the AD5700-1 does not fall below GND during a 25 Hz, 4 mA to 20mA input signal (representing the fastest allowable slew rate for a HART-enabled device).

Power Supply Circuit

The evaluation board is powered by a 5.5 V to 36 V dc power supply and uses an on-board switching regulator to provide the 5 V supply to the system, as shown in Figure 5. In the test setup, the 5 V also powers the EVAL-SDP-CB1Z system demonstration platform (SDP) board. The EVAL-SDP-CB1Z SDP board provides a regulated 3.3 V for the VIO voltage.

The high switching frequency of the ADP2441 allows minimal output voltage ripple even when small inductors are used. Selecting the size of the inductor involves considering the trade-off between efficiency and transient response. A smaller inductor results in larger inductor current ripple, which provides excellent transient response but degrades efficiency. Due to the high switching frequency of the ADP2441, using shielded ferrite core inductors is recommended because of their low core losses and low electromagnetic interference (EMI).

In the Figure 5 circuit, the switching frequency is approximately 1 MHz with the 88.7 kΩ external resistor. The inductor value of 12 μH (Coilcraft LPS6235-123MLC) is chosen from Table 8 of the ADP2441 data sheet.

The circuit is connected to the field supply of 5.5 V to 36 V using screw terminals. The EARTH terminal can be connected to an external earth connection or to the GND terminal if an external earth connection is not used.

Power inductors (DR73-102-R), varistors (V56ZA3P, 56 V), power diode (S2A-TP, 50 V), and a 1.1 A fuse provide additional input protection against high voltage transient events.

Noise Test

Evaluate the system noise by shorting the input terminals for each channel, which results in a zero differential voltage for the voltage input channels and grounded input for the current input channels. Gather the data with the inputs shorted, and compute the code spread and noise-free code resolution from the set number of samples.

This noise test can be done using the CN-0364 Evaluation Software. The code spread and noise-free code resolution of each channel can be obtained and the data displayed in a histogram. Figure 6 shows a histogram from sample data gathered from the voltage input of Channel 1.

HART Testing

The HART functionality was tested according to the HART physical layer test specification (HCF-TEST-2). The circuit met the requirements for the HART physical layer. More details on the HART specifications can be obtained directly from the HART Communication Foundation.

The rejection of the ADC input to the HART 1.2 kHz and 2.2 kHz signals was also measured. Table 3 shows the results.

A complete design support package for the EVAL-CN0364-SDPZ board including schematic, bill of materials, and layout can be downloaded from www.analog.com/CN0364-DesignSupport.