AD9643

RECOMMENDED FOR NEW DESIGNS

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

Data Sheet (Rev. G) Product Selection Table
Part Models
6
1ku List Price
Starting From $93.08
Viewing:

Part Details

  • SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS
  • SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
  • −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS
  • Total power consumption: 785 mW at 250 MSPS
  • 1.8 V supply voltages
  • LVDS (ANSI-644 levels) outputs
  • Integer 1-to-8 input clock divider (625 MHz maximum input)
  • Sample rates of up to 250 MSPS
  • IF sampling frequencies of up to 400 MHz
  • Internal ADC voltage reference
  • Flexible analog input range
    • 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
  • ADC clock duty cycle stabilizer
  • 95 dB channel isolation/crosstalk
  • Serial port control
  • Energy saving power-down modes
AD9643
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9643 Functional Block Diagram AD9643 Pin Configuration 1 AD9643 Pin Configuration 2
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project
Ask a Question

Documentation

Data Sheet 1

User Guide 1

Application Note 16

Technical Articles 2

Evaluation Design File 3

Learn More
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project

Software Resources

Device Drivers 1

Hardware Ecosystem

Parts Product Life Cycle Description
Clock Distribution Devices 3
AD9513
RECOMMENDED FOR NEW DESIGNS 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514
RECOMMENDED FOR NEW DESIGNS 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515
RECOMMENDED FOR NEW DESIGNS 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
Clock Generation Devices 6
AD9523
NOT RECOMMENDED FOR NEW DESIGNS 14-Output, Low Jitter Clock generator
AD9523-1
RECOMMENDED FOR NEW DESIGNS Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9524
NOT RECOMMENDED FOR NEW DESIGNS 6 Output, Dual Loop Clock Generator
AD9510
RECOMMENDED FOR NEW DESIGNS 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
AD9511
RECOMMENDED FOR NEW DESIGNS 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9512
RECOMMENDED FOR NEW DESIGNS 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
Digital Control VGAs 2
ADL5202
Obsolete Wide Dynamic Range, High Speed, Digitally Controlled VGA
AD8376
RECOMMENDED FOR NEW DESIGNS Ultralow Distortion IF Dual VGA
Fully Differential Amplifiers 1
ADL5562
RECOMMENDED FOR NEW DESIGNS 3.3 GHz Ultralow Distortion RF/IF Differential Amplifier
Single-Ended to Differential Amplifiers 2
ADA4927-2
RECOMMENDED FOR NEW DESIGNS Ultralow Distortion Current Feedback Differential ADC Driver
ADA4938-2
RECOMMENDED FOR NEW DESIGNS Ultralow Distortion Differential ADC Driver (Dual)
Modal heading
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Open Tool

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

Open Tool

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

S-Parameter 1

AD9643 IBIS Model 1

AD9643 Simulink ADIsimADC Model

Open Tool

Evaluation Kits

eval board
schematic 1
HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Buy Now View Details

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Details

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

eval board
schematic 2
schematic 3
schematic 4
EVAL-AD9643

AD9643 Evaluation Board

Buy Now View Details

Features and Benefits

  • Full featured evaluation board for the AD9643/AD9613/AD6649/AD6643
  • SPI interface for setup and control
  • External or AD9523 clocking option
  • Balun/transformer or amplifier input drive options
  • LDO regulator power supply
  • VisualAnalog and SPI controller software interfaces

Product Details

The AD9643-250EBZ is an evaluation board for the AD9643, dual 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9643.

The AD9643 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.
HSC-ADC-EVALCZ
FPGA-Based Data Capture Kit
High_Speed_ADC_evalboard_05
EVAL-AD9643
AD9643 Evaluation Board
AD9643-250EBZ Evaluation Board AD9643-250EBZ Evaluation Board - Top View AD9643-250EBZ Evaluation Board - Bottom View

Reference Designs

Single Channel of Quad IF Receiver Front End
Single Channel of Quad IF Receiver Front End
CN0242 Circuits from the lab

High Performance, High IF, 75 MHz Bandwidth, 14-Bit, 250 MSPS Receiver Front End with Band-Pass Antialiasing Filter

View Detailed Reference Design

Features and Benefits

  • 14-bit, 250MSPS Receiver Front End
  • Bandpass antialiasing filter
  • Digitally controlled VGA
CN0242
High Performance, High IF, 75 MHz Bandwidth, 14-Bit, 250 MSPS Receiver Front End with Band-Pass Antialiasing Filter
Single Channel of Quad IF Receiver Front End

Latest Discussions

8 Weeks Ago
RE: Regarding AD9643 source code to interface the data output with FPGA ( Xilinx virtex)
15 Weeks Ago
Buffer capable failure for 2nd ADRV9002
View related discussion on EngineerZone®

Recently Viewed