The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth,
and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each ADC
features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for
variations in the ADC clock duty cycle, allowing the converters to
maintain excellent performance.
ADC data outputs are internally connected directly to the digital
downconverter (DDC) of the receiver. The digital receiver has two
channels and provides processing flexibility. Each receive channel
has four cascaded signal processing stages: a 32-bit frequency
translator (numerically controlled oscillator (NCO)), an optional
sample rate converter, a fixed FIR filter, and an fS/4 fixed-frequency
NCO.
n addition to the receiver DDC, the AD6649 has several functions
that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits
of the ADC. If the input signal level exceeds the programmable
threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the
system gain to avoid an overrange condition at the ADC input.
After digital processing, data is routed directly to the 14-bit output
port. These outputs operate at ANSI or reduced swing LVDS signal
levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods. In
diversity applications, the output data format is real due to the final
NCO, which shifts the output center frequency to fS/4.
Flexible power-down options allow significant power savings, when
desired.
Programming for setup and control is accomplished using a 3-pin
SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product is
protected by a U.S. patent.
Applications
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
- General-purpose software radios
- Broadband data applications
Product Highlights
- Integrated dual, 14-bit, 250 MSPS ADC.
- Integrated wideband decimation filter and 32-bit
complex NCO.
- Fast overrange and threshold detect.
- Proprietary differential input maintains excellent SNR
performance for input frequencies up to 300 MHz.
- SYNC input allows synchronization of multiple devices.
- 3-pin, 1.8V SPI port for register programming and register
readback.
