AD9558
RECOMMENDED FOR NEW DESIGNSQuad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync
Part Details
- Supports GR-1244 Stratum 3 stability in holdover mode
- Supports smooth reference switchover with virtually no disturbance on output phase
- Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
- Supports ITU-T G.8262 synchronous Ethernet subordinate clocks
- Supports ITU-T G.823, G.824, G.825, and G.8261
- Auto/manual holdover and reference switchover
- 4 reference inputs (single-ended or differential)
- Input reference frequencies: 2 kHz to 1250 MHz
- Reference validation and frequency monitoring (1 ppm)
- Programmable input reference switchover priority
- 20-bit programmable input reference divider
- 6 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
- Output frequencies: 352 Hz to 1250 MHz
- Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
- Programmable digital loop filter covering loop bandwidths from 0.1Hz to 5 kHz (2 kHz maximum for <0.1 dB of peaking)
- Low noise system clock multiplier
- Frame sync support
- Adaptive clocking
- Optional crystal resonator for system clock input
- On-chip EEPROM to store multiple power-up profiles
- Pin program function for easy frequency translation configuration
- Software controlled power-down
- 64-lead, 9 mm × 9 mm, LFCSP package
The AD9558 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9558 generates an output clock synchronized to up to four external input references. The digital phase-locked loop (PLL) allows reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9558 continuously generates a low jitter output clock even when all reference inputs have failed.
The AD9558 operates over an industrial temperature range of −40°C to +85°C. If a smaller package is required, refer to the AD9557 for the two-input/two-output version of the same device.
Applications
- Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping
- Cleanup of reference clock jitter
- SONET/SDH/OTN clocks up to 100 Gbps, including FEC
- Stratum 3 holdover, jitter cleanup, and phase transient control
- Wireless base station controllers
- Cable infrastructure
- Data communications
Documentation
Data Sheet 1
Product Selection Guide 1
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
Parts | Product Life Cycle | Description |
---|---|---|
Clock Distribution Devices 8 | ||
AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
ADCLK925 | RECOMMENDED FOR NEW DESIGNS | Ultrafast SiGe ECL Clock/Data Buffers |
ADCLK944 | RECOMMENDED FOR NEW DESIGNS | 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer |
ADCLK948 | RECOMMENDED FOR NEW DESIGNS | Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer |
ADCLK854 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer |
ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
Clock Generation Devices 1 | ||
AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
External Power Switch Buck Controllers 1 | ||
ADP1829 | PRODUCTION | Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking |
Positive Linear Regulators (LDO) 1 | ||
ADP150 | PRODUCTION | Ultralow Noise, 150 mA CMOS Linear Regulator |