CN0372

This circuit provides an optimized low power compact solution for multichannel system monitoring. These characteristics are particularly important in wearable and self-powered applications where form factor and power consumption are critical system specifications.

Analog-to-Digital Converter

The AD7091R-5 is a 12-bit, ultralow power, successive approximation ADC. The device operates from a single 2.7 V to 5.25 V power supply. This ADC features an on-chip conversion clock, an accurate reference, and an I²C interface that operates in both standard (f_SCL = 100 kHz) and fast (f_SCL = 400 kHz) modes.

The conversion process and data acquisition are controlled using the I²C interface and an internal oscillator. The AD7091R-5 interface allows data read after the conversion, achieving a maximum 22.22 kSPS throughput rate in fast mode. This device uses advanced design and process techniques to achieve ultralow power dissipation without compromising performance. An on-chip, accurate 2.5 V reference is available on the REF_IN/REF_OUT pin.

The AD7091R-5 has an autocycle mode that allows the user to configure the ADC for autonomous operation and is ideal for the monitoring of events outside of a user defined range. Conversions automatically take place at configured intervals as shown in Table 25 of the AD7091R-5 data sheet. Typically, this mode is used to monitor a selection of channels with limit registers programmed to signal out of bounds conditions via the alert function.

Energy Harvester

The ADP5090 is an integrated boost regulator that converts dc power from photovoltaic cells or thermoelectric generators. The device charges storage elements (rechargeable battery or super capacitor). The CN-0372 board uses a super capacitor that supplies power for small electronic devices and battery-free systems. The ADP5090 provides efficient conversion of the small amounts of harvested power available from PV cells or TEGs. The ADP5090 operates on an input power range from 16 μW to 200 mW range with sub-microwatt operation losses.

With the internal cold-start circuit, the regulator can start operating at an input voltage as low as 380 mV. This solution eliminates the need for an external battery to power the circuit (although backup battery options are available) and makes full use of harvestable energy instead.

The SYS voltage output of the ADP5090 supplies the entire circuit as shown in Figure 1.

Circuit Design

The circuit in Figure 2 shows the minimal connections needed for the AD7091R-5 ADC.

The analog input range for the AD7091R-5 is 0 V to V_REF and is unipolar. The circuit is not designed to accept negative voltages. While the AD7091R-5 contains a wide bandwidth track-and-hold amplifier that can handle input frequencies up to 1.5 MHz, the circuit is tested to resolve lower frequencies up to 2 kHz in fast mode.

The AD7091R-5 provides access to the multiplexer output eliminating the need for a signal conditioning circuit in each channel when additional filtering is required. The input signal of the active channel appears at MUX_OUT. The filters before the ADC V_IN pins are designed to have a cutoff frequency of about 8.6 MHz. These filters attenuate noise at the ADC input and absorb the charge kickbacks from the ADC. It is recommended to use a low series resistance value and a reasonably sized capacitor that can source and sink the high frequency charge kickbacks from the ADC.

If no additional filtering or signal conditioning is required, the MUX_OUT pin is tied directly to ADC_IN. Control of the AD7091R-5 is through the I²C-compatible serial bus.

Figure 3 shows the ADP5090 energy harvesting circuit. The circuit converts power from an energy source connected to the J4 terminal, stores charge in the super capacitor (C26), and provides power to the entire circuit.

Harvested energy from a PV cell or TEG is introduced at ENERGY_IN. When ENERGY_IN exceeds 380 mV, the ADP5090 enters cold start-up. The device then exits cold-startup, and main boost is enabled when the SYS voltage exceeds V_{SYS_TH}, which is typically 1.93 V. The logic high level on PGOOD is equal to the SYS voltage, and when the battery terminal voltage is reached, the main boost charger is turned off.

The ADP5090 boost regulator operates in pulse frequency mode (PFM), transferring energy stored in the input capacitor to SYS and the C26 super capacitor (Cellergy CLG03P050F17, 50 mF, 3.5 V). A PGOOD threshold is set by external connectors to indicate that the SYS voltage is at an acceptable voltage, given by

where:

R_PG1 and R_PG2 are the values from Figure 3.
V_{REF_ADP5090} is typically 1.21 V.

The ADP5090 is also equipped with battery overcharging and discharging protection thresholds, which are also set by external resistors.

To prevent overcharging, the rising threshold for the battery terminal voltage is given by

where R_TERM1 and R_TERM2 are the values from Figure 3.

To prevent deep discharge, the falling threshold for the battery discharge shutdown voltage is given by

where R_SD1 and R_SD2 are the values from Figure 3.

An illustration of these threshold voltages is shown in Figure 4.

The circuit in Figure 3 also has a provision through SL7 to provide a low energy state backup option to accelerate cold-start.

A complete documentation package including schematics, board layout, and bill of materials (BOM) can be found at www.analog.com/CN0372-DesignSupport. The circuit is compatible with the Digilent PMOD interface standard.

Measurement Results for DAS with Energy Harvesting Circuit

The circuit comes with a graphical user interface that facilitates configuring the devices on-board and evaluating the circuit performance. Tabs are available for device configuration, as well as for displaying noise performance, histogram, and register readout. For a complete description of the software package, see the CN-0372 Software User Guide.

Figure 5 and Figure 6 show the ac performance of the circuit, configured with MUX_OUT connected directly to ADC_IN, for a 2.4 V p-p, 1 kHz sine wave with a common-mode voltage of 1.25 V. While the default configuration generates a 3.3 V supply on SYS, all measurements in this circuit note were taken with the external resistors configured for 3 V supplies.

Power consumed is computed using the following equation:

where:

The circuit, configured without the buffer and with V_DD and V_DRIVE coming from SYS, consumes 34 μA.