AD9559

RECOMMENDED FOR NEW DESIGNS

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

Part Details

  • Supports GR-1244 Stratum 3 stability in holdover mode
  • Supports smooth reference switchover with virtually no disturbance on output phase
  • Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
  • Supports ITU-T G.8262 synchronous Ethernet node clocks
  • Supports ITU-T G.823, G.824, G.825, and G.8261
  • Auto/manual holdover and reference switchover
  • Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
  • Dual digital PLL architecture with four reference inputs (single-ended or differential)
  • 4x2 crosspoint allows any reference input to drive either PLL
  • Input reference frequencies from 2 kHz to 1250 MHz
  • Reference validation and frequency monitoring (2 ppm)
  • Programmable input reference switchover priority
  • 20-bit programmable input reference divider
  • 4 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
  • Output frequencies: 262 kHz to 1250 MHz
  • Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
  • Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 2 kHz
  • Low noise system clock multiplier
  • Optional crystal resonator for system clock input
  • On-chip EEPROM to store multiple power-up profiles
  • Pin program function for easy frequency translation configuration
  • Software controlled power-down
  • 72-lead (10 mm × 10 mm) LFCSP package
AD9559
Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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Hardware Ecosystem

Parts Product Life Cycle Description
Clock Distribution Devices 8
ADCLK925 RECOMMENDED FOR NEW DESIGNS Ultrafast SiGe ECL Clock/Data Buffers
ADCLK944 RECOMMENDED FOR NEW DESIGNS 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948 RECOMMENDED FOR NEW DESIGNS Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer
ADCLK854 RECOMMENDED FOR NEW DESIGNS 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
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Tools & Simulations

IBIS Model 1


Evaluation Kits

eval board
EVAL-AD9559

AD9559 Evaluation Board

Product Details

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates two completely independent output clocks that are synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

For convenience, detailed information from the AD9559 data sheet has been included here. Use this user guide in conjunction with the AD9559 data sheet and software documenta¬tion available at www.analog.com.


Features
  • Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
  • LDOs are easily bypassed for power measurements
  • 4 ac-coupled differential output SMA connectors (which can be reconfigured for up to 8 single-ended outputs.
  • 4 inputs SMA connectors that accept either single-ended or differential signals
  • USB connection to PC
  • Microsoft Windows-based evaluation software with simple graphical user interface and support for both 64-bit and 32-bit operating systems.
  • Easy access to digital I/O and diagnostic signals via I/O header
  • Status LEDs for diagnostic signals

EVAL-AD9559
AD9559 Evaluation Board

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