AD9887A
新規設計には非推奨Dual Interface for Flat Panel Display
- 製品モデル
- 3
- 1Ku当たりの価格
- 最低価格:$15.46
製品の詳細
ANALOG INTERFACE
- 170 MSPS maximum conversion rate
- Programmable analog bandwidth
- 0.5 V to 1.0 V analog input range
- 500 ps p-p PLL clock jitter at 170 MSPS
- 3.3 V power supply
- Full sync processing
- Midscale clamping
- 4:2:2 output format mode
DIGITAL INTERFACE
- DVI 1.0-compatible interface
- 170 MHz operation (2 pixels/clock mode)
- High skew tolerance of 1 full input clock
- Sync detect for hot plugging
- Supports high bandwidth digital content protection
The AD9887A offers an analog interface receiver and a digital visual interface (DVI) receiver integrated on a single chip, supports high bandwidth digital content protection (HDCP), and is software and pin-to-pin compatible with the AD9887.
ANALOG INTERFACE
The complete 8-bit, 170 MSPS, monolithic analog interface is optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 330 MHz support resolutions of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes a 170 MHz triple ADC with internal 1.25 V reference; a phase-locked loop (PLL); and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The analog interface also offers full sync processing for composite sync and sync-on-green (SOG) applications. The AD9887A on-chip PLL generates a pixel clock from Hsync with output frequencies ranging from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps p-p at 170 MSPS.
DIGITAL INTERFACE
The AD9887A contains a DVI 1.0-compatible receiver and supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The receiver operates with true color (24-bit) panels in one or two pixel(s) per clock mode and features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can receive encrypted video content. The AD9887A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of authentication during transmission, as specified by the HDCP v1.0 protocol. Fabricated in an advanced CMOS process, the AD9887A is provided in a 160-lead, surface-mount, plastic MQFP and is specified over the 0°C to 70°C temperature range. The AD9887A is also available in an RoHS compliant package.
APPLICATIONS
- RGB graphics processing
- LCD monitors and projectors
- Plasma display panels
- Scan converters
- Microdisplays
- Digital TVs
ドキュメント
データシート 1
アプリケーション・ノート 1
技術記事 1
製品ハイライト 1
製品ハイライト 1
製品モデル | ピン/パッケージ図 | 資料 | CADシンボル、フットプリント、および3Dモデル |
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AD9887AKSZ-100 | 160-Lead MQFP | ||
AD9887AKSZ-140 | 160-Lead MQFP | ||
AD9887AKSZ-170 | 160-Lead MQFP |
製品モデル | 製品ライフサイクル | PCN |
---|---|---|
10 18, 2016 - 16_0034 Assembly Relocation of Select LQFP,LQFP_EP,MQFP,TQFP,TQFP_EP Products to Stats ChipPAC China Jiangyin |
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AD9887AKSZ-100 | 製造中 | |
AD9887AKSZ-140 | 製造中 | |
AD9887AKSZ-170 | 製造中 | |
3 10, 2010 - 10_0017 QFP Multigrade Laser Conversion |
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AD9887AKSZ-100 | 製造中 | |
AD9887AKSZ-140 | 製造中 | |
AD9887AKSZ-170 | 製造中 | |
8 19, 2009 - 07_0024 Package Material Changes for SOT23, MiniSO, MQFP, PDIP, PLCC, SOIC (narrow and wide body), SSOP, TSSOP and TSSOP exposed pad |
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AD9887AKSZ-100 | 製造中 | |
AD9887AKSZ-140 | 製造中 | |
AD9887AKSZ-170 | 製造中 | |
1 5, 2009 - 07_0077 Certification of STATSChipPAC Shanghai, China and AMKOR Philippines as additional sources for Assembly & Test of QFP Packages |
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AD9887AKSZ-100 | 製造中 | |
AD9887AKSZ-140 | 製造中 | |
AD9887AKSZ-170 | 製造中 |
これは最新改訂バージョンのデータシートです。
ソフトウェア・リソース
評価用ソフトウェア 1
ハードウェア・エコシステム
製品モデル | 製品ライフサイクル | 詳細 |
---|---|---|
ADV7842 | 新規設計に推奨 | デュアルHDMI1.4スイッチング・レシーバ、ビデオ/グラフィックス・デジタイザおよび3Dコンボ・フィルタ・デコーダ付、12ビット、170MHZ |