CN0360

The detector circuit consists of an rms detector, a variable gain amplifier (VGA), a SAW filter, a mixer, and a frequency synthesizer that combine to provide a 90 dB detection range and excellent stability vs. frequency and temperature. Figure 2 shows the transfer function of the detector circuit when the input power is swept at 900 MHz. Optimum linearity is achieved using a four point calibration with calibration points at +13 dBm, −50 dBm, −65 dB, and −75 dBm. A two point calibration can also be used, but results in degraded linearity across the input power range.

The ADL5902 detector used in the circuit inherently provides 65 dB of detection range from 50 MHz to 9 GHz. The AD8368 VGA extends the upper and the lower end of the power range. The narrow-band SAW filter placed between the VGA and the detector maximizes the low end sensitivity by filtering noise from the VGA and the mixer. The Circuit Note CN-0340 describes this dynamic range extension mechanism in additional detail.

However, this range extension limits operation at the pass-band frequency range of the filter. Coupling the CN-0360 circuit with a wideband frequency translation network makes the combined circuit frequency-selective. In the circuit shown in Figure 1, the ADL5801 mixer is paired with the ADF4351 frequency synthesizer to translate input signals from 35 MHz to 4.4 GHz to 140 MHz, the pass-band frequency of the SAW filter. The Circuit Note CN-0239 describes the glueless broadband mixer and local oscillator interface used in the circuit.

The circuit dynamic range was further enhanced by optimizing the mixer bias level using the VSET pin on the ADL5801 mixer. Typically, the ADL5801 mixer is operated at a VSET level of 3.6 V, resulting in high mixer bias and correspondingly high IP3. However, this operating point results in noise figure degradation, limiting input sensitivity. Operating the mixer at the minimum VSET level of 2.0 V improves mixer noise figure, but the P1dB of the mixer suffers as a result, limiting the dynamic range at the top end. The adaptive bias mechanism of the mixer is used to optimize the circuit detection range at both high and low power levels. By connecting the VSET pin to DETO, a pin routed to the internal power detector of the mixer, the device bias level is set adaptively based on signal conditions. This feature allows the mixer to provide high linearity and compression in the presence of large RF signals, and low noise figure in the presence of small RF signals. Implementing this feature improves the application sensitivity at lower input power levels, while also maintaining the dynamic range at the higher input power levels. Figure 3 shows the transfer function of the detector with various mixer bias levels.

Temperature Stability

Figure 2 shows the temperature stability of the detector vs. RF input power across the power spectrum. The accuracy over temperature was achieved using the temperature compensation feature on the ADL5902 rms detector to account for the temperature drift introduced into the system. Any temperature variation in the gain of the VGA and the mixer degrades the overall drift of the circuit one for one (that is, a 1 dB drift vs. temperature in the gain of the mixer degrades the overall temperature stability by 1 dB). In the case of the AD8368 VGA, Figure 5 in the AD8368 data sheet shows that the gain drift over temperature is approximately ±0.7 dB. Similarly, according to Figure 3 in the ADL5801 data sheet, the mixer drift over temperature is ±0.5 dB. Adjusting the voltage on the ADL5902 TADJ pin compensates for the combined temperature drift of the detector, VGA, and mixer. It was experimentally determined that a TADJ voltage of 0.6 V provides optimum temperature compensation at all RF input frequencies.

Frequency Stability

Figure 4 and Figure 5 display the circuit frequency flatness. The circuit exhibits approximately 1 dB flatness across the complete operating frequency range. Because the mixer downconverts input signals to 140 MHz, the gain variation introduced by the mixer dominates the frequency flatness profile.

Blocker Immunity

Figure 6 displays the performance of the circuit at 900 MHz when an unwanted blocking signal at 960 MHz is present. The blocking signal was placed 60 MHz away from carrier signal because the filter exhibits poor pass-band rejection at that frequency (see Figure 7), thus presenting the harshest test condition for the circuit. The blocking signal degrades the lower end sensitivity of the circuit for blocker input levels above −10 dBm; however, the circuit continues to maintain 65 dB of dynamic range for blocking signals of up to +5 dBm.