CN0187

The RF signal being measured is applied to the ADL5502. A single 75 Ω termination resistor at the RF input in parallel with the input impedance of the ADL5502 provides a broadband match of 50 Ω. More precise resistive or reactive matches can be applied for narrow frequency band use (see the RF Input Interfacing section of the ADL5502 data sheet).

The internal filter capacitor of the ADL5502 provides averaging in the square domain but leaves some residual ac on the output. Signals with high peak-to-average ratios, such as W-CDMA or CDMA2000, can produce ac residual levels on the ADL5502 VRMS dc output. To reduce the effects of these low frequency components in the waveforms, some additional filtering is required. The internal square-domain filter capacitance of the ADL5502 can be augmented by connecting a CFLTR capacitor between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be reduced further by adding capacitance to the VRMS output. The combination of the internal 100 Ω output resistance and the added output capacitance produces a low-pass filter to reduce output ripple of the VRMS output (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section of the ADL5502 data sheet for more details).

To measure the peak of a waveform, the control line (CNTL) must be temporally set to a logic high (reset mode for >1 μs) and then set back to a logic low (peak-hold mode). This allows the ADL5502 to be initialized to a known state. When setting the device to measure peak, peak-hold mode should be toggled for a period in which the input rms power and crest factor (CF) is not likely to change.

If the ADL5502 is in peak-hold mode and the CF changes from high to low or the input power changes from high to low, a faulty peak measurement is reported. The ADL5502 simply keeps reporting the highest peak that occurred when the peakhold mode was activated and the input power or the CF was high. Unless CNTL is reset, the PEAK output does not reflect the new peak in the signal.

The ADL5502 is capable of sourcing a VRMS output current of approximately 3 mA. The output current is sourced through the on-chip, 100 Ω series resistor; therefore, any load resistor forms a voltage divider with this on-chip resistance. It is recommended that the ADL5502 VRMS output drive high resistive loads to preserve output swing. If an application requires driving a low resistance load (as well as in cases where increasing the nominal conversion gain is desired), a buffering circuit is necessary.

The PEAK output is designed to drive 2 pF loads. It is recommended that the ADL5502 PEAK output drive low capacitive loads to achieve a full output response time. The effects of larger capacitive loads are particularly visible when tracking envelopes during the falling transitions. When the envelope is in a fall transition, the load capacitor discharges through the on-chip load resistance of 1.9 kΩ. If the larger capacitive load is unavoidable, the additional capacitance can be counteracted by putting a shunt resistor to ground on the PEAK output to allow for fast discharge. Such a shunt resistor also makes the ADL5502 run higher current, and it should not be lower than 500 Ω.

Typical measured performance characteristics of the circuit are presented in Figure 2 through Figure 5.

The turn-on time and pulse response is strongly influenced by the size of the square-domain filter (C_FLTR) and output shunt capacitor connected to the VRMS output. Figure 6 (taken from the ADL5502 data sheet) shows a plot of the output response to an RF pulse on the RFIN pin, with a 0.1 μF output filter capacitor and no square-domain filter capacitor (C_FLTR). The falling edge is particularly dependent on the output shunt capacitance.

To improve the falling edge of the enable and pulse responses, a resistor can be placed in parallel with the output shunt capacitor. The added resistance helps to discharge the output filter capacitor. Although this method reduces the power-off time, the added load resistor also attenuates the output (see the Output Drive Capability and Buffering section of the ADL5502 data sheet). Figure 7 (taken from the ADL5502 data sheet) shows the improvement obtained by adding a parallel 1 kΩ resistor.

The RMS and PEAK outputs of the ADL5502 pass through unity gain buffers that drive cross-coupled stages for converting the single-ended outputs to differential signals. The internal +2.5 V reference of the AD7266 (via the D_CAPA and D_CAPB pins) passes through another unity gain buffer and a voltage divider. This sets the common-mode voltage of the network to +1.25 V.

The AD7266 achieves simultaneous samples of the RMS and PEAK outputs and transfers the data within a 1 μs response time. The data is provided on a single serial data line. Because slope and intercept vary from device to device, board-level calibration must be performed to achieve high accuracy. In general, calibration is performed by applying two input power levels to the ADL5502 and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear operating range of the device. The best-fit line is characterized by calculating the conversion gain (or slope) and intercept using the following equations:

where:

V_IN is the rms input voltage to RFIN.
V_VRMS is the voltage output at VRMS.

Once gain and intercept are calculated, an equation can be written that allows calculation of an (unknown) input power based on the measured output voltage.

For an ideal (known) input power, the law conformance error of the measured data can be calculated as

Figure 8 and Figure 9 show plots of the VRMS and PEAK error at 25°C, the temperature at which the ADL5502 is calibrated. Note that the error is not zero; this is because the ADL5502 does not perfectly follow the ideal linear equation, even within its operating region. The error at the calibration points is, however, equal to zero by definition.

When the characteristics (slope and intercept) of the VRMS and PEAK outputs are known, the calibration for the CF calculation is complete. A three-stage process must be taken to measure and calculate the crest factor of any waveform. First, the unknown signal must be applied to the RF input, and the corresponding VRMS level is measured. This level is indicated in Figure 10 as V_VRMS-UNKNOWN. The RF input, V_IN, is calculated using V_VRMS-UNKNOWN and Equation 3.

Next, the CW reference level of PEAK, VPEAK-CW, is calculated using V_IN (that is, the output voltage that would be seen if the incoming waveform was a CW signal).

Finally, the actual level of PEAK, V_PEAK-UNKNOWN, is measured and the CF can be calculated as

where V_PEAK-CW is used as a reference point to compare V_PEAK-UNKNOWN. If both V_PEAK values are equal, then the CF is 0 dB, as shown in Figure 11 with the CW signal (taken from the ADL5502 data sheet). Across the dynamic range, the calculated CF hovers about the 0 dB line. Likewise, for complex waveforms of 3 dB, 6 dB, and 9 dB CFs, the calculations accurately hover about the corresponding CF levels.

The performance of this or any high speed circuit is highly dependent on proper PCB layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where required), component placement, signal routing, and power and ground planes. (See MT-031 Tutorial, MT-101 Tutorial, and article, A Practical Guide to High-Speed Printed-Circuit-Board Layout, for more detailed information regarding PCB layout.) A complete design support package for this circuit note can be found at http://www.analog.com/CN0187-DesignSupport.