AD9577
RECOMMENDED FOR NEW DESIGNSClock Generator with Dual PLLs, Spread Spectrum, and Margining
- Part Models
- 3
- 1ku List Price
- Starting From $5.57
Part Details
- Fully integrated dual PLL/VCO cores
- 1 integer-N and 1 fractional-N PLL
- Continuous frequency coverage from 11.2 MHz to 200 MHz
- Most frequencies from 200 MHz to 637.5 MHz available
- PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical
- PLL2 phase jitter (12 kHz to 20 MHz)
- Integer-N mode: 470 fs rms typical
- Fractional-N mode: 660 fs rms typical
- Input crystal or reference clock frequency
- Optional reference frequency divide-by-2
- I2C programmable output frequencies
- Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks
- 1 CMOS buffered reference clock output
- Spread spectrum: downspread [0, −0.5]%
- 2 pin-controlled frequency maps: margining
- Integrated loop filters
- Space saving, 6 mm × 6 mm, 40-lead LFCSP package
- 1.02 W power dissipation (LVDS operation)
- 1.235 W power dissipation (LVPECL operation)
- 3.3 V operation
The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining. Other applications with demanding phase noise and jitter requirements can benefit from this part.
The first integer-N PLL section (PLL1) consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), a programmable feedback divider, and two independently programmable output dividers. By connecting an external crystal or applying a reference clock to the REFCLK pin, frequencies of up to 637.5 MHz can be synchronized to the input reference. Each output divider and feedback divider ratio is I2C programmed for the required output rates.
A second fractional-N PLL (PLL2) with a programmable modulus allows VCO frequencies that are fractional multiples of the reference frequency to be synthesized. Each output divider and feedback divider ratio can be programmed for the required output rates, up to 637.5 MHz. This fractional-N PLL can also operate in integer-N mode for the lowest jitter.
Up to four differential output clock signals can be configured as either LVPECL or LVDS signaling formats. Alternatively, the outputs can be configured for up to eight CMOS outputs. Combinations of these formats are supported. No external loop filter components are required, thus conserving valuable design time and board space. The AD9577 is available in a 40-lead, 6 mm × 6 mm LFCSP package and can operate from a single 3.3 V supply. The operating temperature range is −40°C to +85°C.
Applications
- Low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital video
- Spread spectrum clocking
Documentation
Data Sheet 1
User Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9577BCPZ | 40-Lead LFCSP (6mm x 6mm w/ EP) | ||
| AD9577BCPZ-R7 | 40-Lead LFCSP (6mm x 6mm w/ EP) | ||
| AD9577BCPZ-RL | 40-Lead LFCSP (6mm x 6mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
May 23, 2014 - 13_0233 Assembly Transfer of Select 6x6 and 7x7mm LFCSP Products to STATS ChipPAC China. |
||
| AD9577BCPZ | PRODUCTION | |
| AD9577BCPZ-R7 | PRODUCTION | |
| AD9577BCPZ-RL | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 8 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| ADCLK925 | RECOMMENDED FOR NEW DESIGNS | Ultrafast SiGe ECL Clock/Data Buffers |
| ADCLK944 | RECOMMENDED FOR NEW DESIGNS | 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK948 | RECOMMENDED FOR NEW DESIGNS | Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer |
| ADCLK854 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer |
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| Clock Generation Devices 1 | ||
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| External Power Switch Buck Controllers 1 | ||
| ADP1828 | PRODUCTION | Synchronous Buck PWM, Step-Down, DC-to-DC Controller |
| Positive Linear Regulators (LDO) 1 | ||
| ADP7104 | RECOMMENDED FOR NEW DESIGNS | 20 V, 500 mA, Low Noise, CMOS LDO |
Evaluation Kits
AD9577 Evaluation Board