AD9553
RECOMMENDED FOR NEW DESIGNSFlexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
- Part Models
- 2
- 1ku List Price
- Starting From $6.55
Part Details
- Input frequencies from 8 kHz to 710 MHz
- Output frequencies up to 810 MHz LVPECL and LVDS (up to 200 MHz for CMOS output)
- Preset pin-programmable frequency translation ratios cover popular wireline and wireless frequency applications, including xDSL, T1/E1, BITS, SONET, and Ethernet.
- Arbitrary frequency translation ratios via SPI port
- On-chip VCO
- Accepts a crystal resonator for holdover applications
- Two single-ended (or one differential) reference input(s)
- Two output clocks (independently programmable as LVDS, LVPECL, or CMOS)
- SPI-compatible, 3-wire programming interface
- Very low power: <450 mW (under most conditions)
- See data sheet for additional features
The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.
The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.
The AD9553 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.
The AD9553 operates over the extended industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators
- Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON
- Wireless infrastructure
- Test and measurement (including handheld devices)
Documentation
Data Sheet 1
Frequently Asked Question 1
Device Drivers 1
Product Selection Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9553BCPZ | 32-Lead LFCSP (5mm x 5mm w/ EP) | ||
| AD9553BCPZ-REEL7 | 32-Lead LFCSP (5mm x 5mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
May 11, 2014 - 13_0231 Assembly Transfer of Select 4x4 and 5x5mm LFCSP Products to STATS ChipPAC China. |
||
| AD9553BCPZ | PRODUCTION | |
| AD9553BCPZ-REEL7 | PRODUCTION | |
|
Aug 30, 2010 - 10_0152 Minor Metal Mask Revision and Datasheet Change on AD9553 |
||
| AD9553BCPZ | PRODUCTION | |
| AD9553BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 0
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 8 | ||
| ADCLK925 | RECOMMENDED FOR NEW DESIGNS | Ultrafast SiGe ECL Clock/Data Buffers |
| ADCLK944 | RECOMMENDED FOR NEW DESIGNS | 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK948 | RECOMMENDED FOR NEW DESIGNS | Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer |
| ADCLK854 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer |
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 1 | ||
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Positive Linear Regulators (LDO) 2 | ||
| ADP150 | PRODUCTION | Ultralow Noise, 150 mA CMOS Linear Regulator |
| ADP151 | PRODUCTION | Ultralow Noise, 200 mA, CMOS Linear Regulator |
Evaluation Kits
AD9553 Evaluation Board