CN0375

The RF transmitter shown in Figure 1 and Figure 2 utilizes the AD9142A TxDAC, the ADRF6720 phase locked loop (PLL)/voltage controlled oscillator (VCO) integrated wideband I/Q modulator, and the ADL5320 ¼ W driver amplifier.

Signal biasing and scaling in the DAC-to-modulator interface circuit is controlled by the four ground referenced resistors (R_BI+, R_BI−, R_BQ+, and R_BQ−) and the two shunt resistors (R_LI and R_LQ), respectively. The input and output matching on the ADL5320 driver amplifier is implemented using shunt capacitors at the input and the output. The required matching components and placement are shown in the ADL5320 data sheet.

The nominal and default value of the AD9142A full-scale output current is 20 mA. This current generates the 500 mV dc bias level and a full-scale output voltage swing of 2 V p-p differential on each DAC output pair with the four ground referenced 50 Ω resistors (R_BI+ = R_BI− = R_BQ+ = R_BQ−). The 2 V p-p voltage swing can be adjusted by the R_L shunt resistors (R_L = R_LI = R_LQ), which are in parallel with the 500 Ω I/Q input impedance of the ADRF6720 modulator. The 500 mV dc bias level is not affected by this adjustment. For example, with a 100 Ω effective differential load, each single-ended output swings between 250 mV and 750 mV but still maintains an average value of 500 mV.

Figure 3 shows the resulting peak-to-peak differential swing as a function of the R_L swing limiting resistor and the 500 Ω parallel differential input impedance.

I/Q Filtering

An antialiasing filter between the DAC and the modulator is necessary to filter out Nyquist images, common-mode noise, and broadband DAC noise. The filter is placed between the dc bias setting resistors and the ac swing-limiting resistor.

The dc bias-setting resistors set the filter source impedance, and the ac swing limiting resistor in parallel with the ADRF6720 500 Ω input impedance sets the filter load impedance.

System Level Simulation

Figure 5 shows the simulated cascaded performance of the DAC, the I/Q modulator and the driver amplifier at 2140 MHz. The AD9142A, ADRF6720, and ADL5320 are well matched in terms of dynamic range and gain. Figure 5 shows 39.4 dBm for composite output third-order intercept (OIP3) and approximately −76 dBc adjacent channel leakage ratio (ACLR) performance. The simulation was done using the ADIsimRF Design Tool.

The linearity of the ADRF6720 can be optimized through the MOD_RSEL (Register 0x31, Bits[12:6]) and MOD_CSEL (Register 0x31, Bits[5:0]) settings. These settings control the amount of antiphase distortion to the baseband input stages to correct for distortion.

Figure 6 through Figure 11 show the measured plots of the output second-order intercept (OIP2) and OIP3 optimization at zero IF, 100 MHz, and 200 MHz complex IF by varying the settings of the MOD_RSEL register and the MOD_CSEL register in the ADRF6720.

Figure 6, Figure 7, and Figure 8 show optimized OIP3 performance every 32 steps on the MOD_RSEL axis; OIP3 performance does not vary significantly as a function of MOD_CSEL at zero IF. However, there is more sensitivity to MOD_CSEL at the higher IF frequencies.

Through MOD_RSEL and MOD_CSEL optimization, OIP3 is approximately 42 dBm at zero IF, 45 dBm at 100 MHz IF, and 48 dBm at 200 MHz IF.

The RSEL and CSEL adjustment do not impact OIP2 performance significantly; however, there is some degradation at high IF frequencies.

Choosing an Output Power Level

While the circuit can achieve output power levels up to 12 dBm, operation at that level is not practical, especially with modulated carriers with high peak-to-average ratios. To achieve an acceptable level of distortion, significant backoff is required. Adjacent channel power ratio (ACPR) has become a popular metric for assessing the system level distortion.

Figure 12 and Figure 13 show the measured ACPR vs. output power at the ADL5320 output for three IF cases in single carrier WCDMA (Test Model 1-64) and LTE (Test Model 1_1 64QAM) cases, respectively. The system achieves an ACPR of approximately −75 dB to −80 dB at the −2 dBm to +6 dBm output power range. In the case of an LTE signal, ACPR is defined as the ratio of the power in the carrier (in a bandwidth of 4.515 MHz) to the power in an adjacent channel (channel spacing = 5 MHz), also measured in a 4.515 MHz bandwidth.

OIP2 and OIP3 can be improved by the MOD_RSEL and MOD_CSEL adjustment shown in the previous section, and accordingly, the ACPR improvement is shown in Figure 13 and Figure 14. The improvement is more noticeable at high output power levels.

The spectrum plots of the single WCDMA and LTE at 2140 MHz are shown in Figure 16 and Figure 17, respectively.

PCB Layout Recommendations

Take special care in the layout of the DAC/modulator/amplifier interface. The following are recommendations for PCB layout:

• Keep all I/Q differential trace lengths well matched.
• Place the filter termination resistors as close as possible to the modulator input.
• Place the DAC output 50 Ω resistors as close as possible to the DAC.
• Use thick trace widths through the filter network to reduce signal loss.
• Place vias around all DAC output traces, filter networks, modulator output traces, LO input traces, amplifier input traces, and amplifier output traces.
• Route LO and modulator outputs on different layers or at 90° angles to each other to prevent coupling.