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HMC511

PRODUCTION

VCO SMT with Fo/2, 9.05 - 10.15 GHz

Data Sheet Product Selection Table

Part Models: 3
1ku List Price: price unavailable

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Part Details

Dual Output: Fo = 9.05 - 10.15 GHz
Fo/2 = 4.525 - 5.075 GHz
Phase Noise: -115 dBc/Hz @100 kHz Typ.

Pout: +13 dBm
No External Resonator Needed
QFN Leadless SMT Package, 25 mm²

Part Models: 3
1ku List Price: price unavailable

Documentation

Data Sheet 1

HMC511 Data Sheet 04/22/2015

Technical Articles 1

High Performance SiGe PLLs Pair with Low Phase Noise GaAs VCOs for Microwave Radio 04/22/2015

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
HMC511LP5	32-Lead QFN (5mm x 5mm w/ EP)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
HMC511LP5E	32-Lead QFN (5mm x 5mm w/ EP)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
HMC511LP5ETR	32-Lead QFN (5mm x 5mm w/ EP)	Material Declaration Reliablity Data	Ultra Librarian SamacSys

Part Models	Product Lifecycle	PCN

Mar 25, 2019 - 19_0017 Obsolete Bulk Packaged Material mistakenly not included in previous Tape and Reel PDNs
		PDN19_0017_Form Material_Report
HMC511LP5	Obsolete	PDN19_0017_Form Material_Report

This is the most up-to-date revision of the Data Sheet.

Tools & Simulations

ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

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