ADRF5045

Quad-MxFE Digitizing Card

• Multi-Channel, Wideband System Development Platform Using MxFE
• Mates With Xilinx VCU118 Evaluation Board (Not Included)
• 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
  • Total 16x 1.5GSPS to 4GSPS ADC
  • 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
  • 16x Programmable Finite Impulse Response Filters (pFIRs)
• 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
  • Total 16x 3GSPS to 12GSPS DAC
  • 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
• Flexible Rx & Tx RF Front-Ends
  • Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
  • Tx: Filtering, Amplification
• On-Board Power Regulation from Single 12V Power Adapter (Included)
• Flexible Clock Distribution
  • On-Board Clock Distribution from Single External 500MHz Reference
  • Support for External Converter Clock per MxFE

16Tx / 16Rx Calibration Board

• Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
• Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
• Combined Tx Channels Out Via SMA Option
• Combined Rx Channels In Via SMA Option
• On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
• On-Board Power Regulation from Single 12V Power Adapter (Included)

Software Features and Benefits
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:

• IIO Oscilloscope GUI
• MATLAB Add-Ons & Example Scripts
• Example HDL Builds including JESD204b/JESD204c Bring-Up
• Embedded Software Solutions for Linux and Device Drivers
• MATLAB System Applications GUI

Software Reference Design Examples for ADEF Applications to Reduce Prototyping Time:

• Multi-Chip Synchronization for Power-Up Phase Determinism
• System-Level Amplitude/Phase Alignment Using NCOs
• Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
• pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
• Fast-Frequency Hopping
• Calibration Board MATLAB Driver File
• FPGA Programming MATLAB Script

The Quad-MxFE System Development Platform contains four MxFE^™ software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.

The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+^™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.

In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.

The system can be used to enable quick time-to-market development programs for applications like:

• ADEF (Phased-Array, RADAR, EW, SATCOM)
• Communications Infrastructure (Multiband 5G and mmWave 5G)
• Electronic Test and Measurement

The ADRF5045-EVALZ is a 4-layer evaluation board. Each copper layer is 0.7 mil (0.5 oz) and separated by dielectric materials.

All RF and dc traces are routed on the top copper layer whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. Top dielectric material is 8 mil Rogers RO4003, offering optimal high frequency performance. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, which allows 2.4 mm RF launchers to be connected at the board edges.

The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with trace width of 14 mil and ground clearance of 5 mil to have a characteristic impedance of 50 Ω. For optimal RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package.

Two power supply ports are connected to the VDD and VSS test points, TP1 and TP4, control voltages are connected to the V1 and V2 test points, TP2 and TP3, and the ground reference is connected to the GND test point, TP5.

On the control traces, V1 and V2, a 0 Ohm resistor is used to connect the test points to the pins on the part. On the supply traces, VDD and VSS, a 100 pF bypass capacitor is used to filter high frequency noise. Additionally, unpopulated components positions are available for applying extra bypass capacitors.

The RF input and output ports (RFC, RF1, RF2, RF3, and RF4) are connected through 50 Ω transmission lines to the 2.4 mm RF launchers, J1 to J5. These high frequency RF launchers are by contact and not soldered onto the board. A thru calibration line connects the unpopulated J6 and J7 launchers; this transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated.