AD9554-1
RECOMMENDED FOR NEW DESIGNSQuad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
- Part Models
- 2
- 1ku List Price
- Starting From $26.72
Part Details
- Supports GR-1244 Stratum 3 stability in holdover mode
- Supports smooth reference switchover with virtually no disturbance on output phase
- Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
- Supports ITU-T G.8262 synchronous Ethernet slave clocks
- Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261
- Auto/manual holdover and reference switchover
- Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
- Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential)
- 4 × 4 crosspoint allows any reference input to drive any PLL
- Input reference frequencies from 2 kHz to 1000 MHz
- Reference validation and frequency monitoring: 2 ppm
- Programmable input reference switchover priority
- 20-bit programmable input reference divider
- 4 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECL-compatible
- Output frequency range: 430 kHz to 941 MHz
- Programmable 18-bit integer and 24-bit fractional feedback divider in digital PLL
- Programmable loop bandwidths from 0.1 Hz to 4 kHz
- 56-lead (8 mm × 8 mm) LFCSP package
The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allow reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554-1 continuously generates a low jitter output clock even when all reference inputs have failed.
The AD9554-1 operates over an industrial temperature range of −40°C to +85°C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of this device is needed, refer to the AD9557 or AD9559, respectively.
Applications
- Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping
- Cleanup of reference clock jitter
- SONET/SDH clocks up to OC-192, including FEC
- Stratum 3 holdover, jitter cleanup, and phase transient control
- Cable infrastructure
- Data communications
- Professional video
Documentation
Data Sheet 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9554-1BCPZ | 56-Lead LFCSP (8mm x 8mm w/ EP) | ||
| AD9554-1BCPZ-REEL7 | 56-Lead LFCSP (8mm x 8mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Aug 1, 2016 - 16_0035 Assembly Relocation of Select LFCSP, Mini-LFCSP and LFCSP Side Solderable Products to STATS ChipPAC China Jiangyin |
||
| AD9554-1BCPZ | PRODUCTION | |
| AD9554-1BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Tools & Simulations
IBIS Model 1
Evaluation Kits
AD9554-1 Evaluation Board