AD9209
RECOMMENDED FOR NEW DESIGNS12-Bit, 4GSPS, JESD204B/C, Quad Analog-to-Digital Converter
- Part Models
- 2
- 1ku List Price
- Starting From $1115.51
Part Details
- Flexible reconfigurable common platform design
- Supports single-, dua-l, and quad-band
- Datapaths and DSP blocks are fully bypassable
- On-chip PLL with multichip synchronization
- External RF clock input option for off-chip PLL
- Supports clock input frequencies up to 12 GHz
- Maximum ADC sample rate up to 4 GSPS
- Maximum data rate up to 4 GSPS using JESD204C
- 8 GHz analog input bandwidth (−3 dB)
- ADC ac performance at 4 GSPS
- Differential input voltage: 1.4 V p-p
- Noise density: −151.5 dBFS/Hz
- HD2: −69 dBFS at 2.7 GHz (AIN at −1 dBFS)
- HD3: −76 dBFS at 2.7 GHz (AIN at −1 dBFS)
- Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz
- Auxiliary features
- Phase coherent fast frequency hopping
- ADC clock driver with selectable divide ratios
- On-chip temperature monitoring unit
- Flexible GPIOx pins
- Versatile digital features
- Selectable decimation filters
- Configurable DDCs
- 8 fine complex DDCs and 4 coarse complex DDCs
- 48-bit NCO per DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Programmable delay per datapath
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
- SERDES JESD204B/JESD204C interface, 8 lanes up to 24.75 Gbps
- 8 lanes per ADCs
- 8 lanes JESD204B/JESD204C Tx (JTx)
- Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
- 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
The AD9209 is a quad, 12-bit, 4 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An on-chip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, simplifying the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.
The quad ADC cores have code error rates (CER) better than 1 × 10−20. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is avail-able for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.
The digital signal processing (DSP) block consisting of two coarse digital down converters (DDCs) and four fine DDCs per pair of ADCs. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).
The AD9209 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, thus allowing for different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.
APPLICATIONS
- Wireless communications infrastructure
- Microwave point-to-point, E-band, and 5G mm wave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Design Note 1
Technical Articles 4
FPGA Interoperability Reports 1
Device Drivers 1
Video Series 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9209BBPZ-4G | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) | ||
| AD9209BBPZRL-4G | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| µModule Buck Regulators 1 | ||
| LTM8053 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 3.5A/6A Step-Down Silent Switcher μModule Regulator |
| Clock Distribution Devices 3 | ||
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| Clock Generation Devices 2 | ||
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| Fully Differential Amplifiers 2 | ||
| ADL5569 | RECOMMENDED FOR NEW DESIGNS | 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier |
| ADL5580 | RECOMMENDED FOR NEW DESIGNS | Fully Differential, 10 GHz ADC Driver with 10 dB Gain |
| Multiple Output Buck Regulators 3 | ||
| LTM4633 | RECOMMENDED FOR NEW DESIGNS | Triple 10A Step-Down DC/DC μModule (Power Module) Regulator |
|
LTM4644 LTM4644-1 |
Quad DC/DC μModule (Power Module) Regulator with Configurable 4A Output Array | |
| LTM4616 | RECOMMENDED FOR NEW DESIGNS | Dual 8A per Channel Low VIN DC/DC μModule (Power Module) Regulator |
| Phase Locked Loop with Integrated VCO 1 | ||
| ADF4377 | RECOMMENDED FOR NEW DESIGNS | Microwave Wideband Synthesizer with Integrated VCO |
| Positive Linear Regulators (LDO) 4 | ||
| ADP1765 | RECOMMENDED FOR NEW DESIGNS | 5 A, Low VIN, Low Noise, CMOS Linear Regulator |
| ADP7158 | RECOMMENDED FOR NEW DESIGNS | 2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator |
| ADM7172 | RECOMMENDED FOR NEW DESIGNS | 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO |
| ADM7150 | RECOMMENDED FOR NEW DESIGNS | 800 mA, Ultra Low Noise/High PSRR LDO |
| Ultralow Noise Regulators 1 | ||
| LTM8063 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 2A Silent Switcher µModule Regulator |
Tools & Simulations
MxFE JESD204 Mode Selector Tool
The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.
Open ToolADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Open ToolS-Parameter 2
AD9207/AD9209 AMI Model
Open ToolThermal Models 1
High Speed Converter Toolbox for MATLAB
Open ToolEvaluation Kits
ADS9-V2EBZ Evaluation Board
Resources
AD9081 Evaluation Board