AD6674

RECOMMENDED FOR NEW DESIGNS

385 MHz BW IF Diversity Receiver

Data Sheet (Rev. D) Product Selection Table
Part Models
6
1ku List Price
Starting From $349.25
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Part Details

  • JESD204B (Subclass 1) coded serial digital outputs
  • In band SFDR = 83 dBFS at 340 MHz (750 MSPS)
  • In band SNR = 66.7 dBFS at 340 MHz (750 MSPS)
  • 1.4 W total power per channel at 750 MSPS (default settings)
  • Noise density = −153 dBFS/Hz at 750 MSPS
  • 1.25 V, 2.5 V, and 3.3 V dc supply operation
  • Flexible input range
    • AD6674-750 and AD6674-1000
      • 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
    • AD6674-500
      • 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
  • 95 dB channel isolation/crosstalk
  • Amplitude detect bits for efficient automatic gain control (AGC) implementation
  • Noise shaping requantizer (NSR) option for main receiver function
  • Variable dynamic range (VDR) option for digital predistortion (DPD) function
  • 2 integrated wideband digital processors per channel
    • 12-bit numerically controlled oscillator (NCO), up to 4 cascaded half-band filters
  • Differential clock inputs
  • Integer clock divide by 1, 2, 4, or 8
  • Energy saving power-down modes
  • Flexible JESD204B lane configurations
  • Small signal dither
AD6674
385 MHz BW IF Diversity Receiver
AD6674 Functional Block Diagram AD6674 Pin Configuration
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Documentation

Data Sheet 1

User Guide 1

Application Note 1

Technical Articles 1

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Software Resources

Evaluation Software 1

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

Hardware Ecosystem

Parts Product Life Cycle Description
Clock Distribution Devices 3
LTC6955
LAST TIME BUY Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family
LTC6953
LAST TIME BUY Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support
HMC7043
RECOMMENDED FOR NEW DESIGNS

High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C
Clock Generation Devices 4
LTC6951
LAST TIME BUY Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO
LTC6952
LAST TIME BUY Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support
HMC7044
RECOMMENDED FOR NEW DESIGNS High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support
AD9528
RECOMMENDED FOR NEW DESIGNS JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs
Digital Control VGAs 1
ADA4961
RECOMMENDED FOR NEW DESIGNS Low Distortion, 3.2 GHz, RF DGA
Fully Differential Amplifiers 1
ADL5565
RECOMMENDED FOR NEW DESIGNS

6 GHz Ultrahigh Dynamic Range Differential Amplifier
Internal Power Switch Buck Regulators 2
ADP2164
RECOMMENDED FOR NEW DESIGNS 6.5V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator
ADP2384
RECOMMENDED FOR NEW DESIGNS 20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator
Positive Linear Regulators (LDO) 1
ADP1741
PRODUCTION 2 A, Low VIN, Dropout, CMOS Linear Regulator
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Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Open Tool

Design Tool 1

ADC Companion Transport Layer RTL Code Generator Tool

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Open Tool

IBIS Model 1

Evaluation Kits

eval board
schematic 1
schematic 2
schematic 3
EVAL-AD6674

AD6674 Evaluation Board

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Features and Benefits

  • Full featured evaluation board for the AD9680 and AD9234
  • SPI interface for setup and control
  • Wide band Balun driven input
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC
  • VisualAnalog® and SPI controller software interfaces

Product Details

The AD6674-1000EBZ is evaluation board for AD6674 385 MHz BW IF Diversity Receiver. The reference designs provide all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD6674. The user guide wiki provides documentation and instructions to configure the device for performance evaluation in the lab.
The AD6674 data sheet provides additional information related to device configuration and performance, and should be consulted when using the evaluation board. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com

EQUIPMENT NEEDED
  • Analog signal source and antialiasing filter
  • Sample Clock Source
  • REFCLOCK source for FPGA receiver
  • PC running Windows 7, XP or Vista
  • USB 2.0 port recommended (USB 1.1 compatible)
  • AD6674-1000EBZ Evaluation Board
  • ADS7-V2EBZ FPGA Based Data Capture Kit
SOFTWARE NEEDED (SUPPLIED ON USB DRIVE)

eval board
schematic 4
ADS7-V2EBZ

FPGA Based Data Capture Kit

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Features and Benefits

  • Based on Virtex-7 FPGA 
  • One (1) FMC-HPC connector 
  • Ten (10) 13.1 Gbps transceivers supported 
  • Two (2) DDR3-1866 DIMMs 
  • Simple USB port interface (2.0)



Product Details

The ADS7-V2 Evaluation Board was developed to support the evaluation of Analog Devices high speed A/D converters, D/A converters and Transceivers with JESD204B bit rates up to 13.1 Gbps. The Quick Start Wiki site listed below provides a high level overview of the platform. In addition, each use case of the board has its own section (e.g. Using the ADS7-V2 for High Speed A/D Converter Evaluation). The ADS7-V2 is intended to be used only with specified Analog Devices Evaluation Boards. The ADS7-V2 is not intended to be used as a development platform, and no support is available for standalone operation. Please refer to Xilinx and its approved distributors for FPGA Development Kits

EVAL-AD6674
AD6674 Evaluation Board
EVAL-AD6674 Evaluation Board EVAL-AD6674 Evaluation Board - Top View EVAL-AD6674 Evaluation Board - Bottom View
ADS7-V2EBZ
FPGA Based Data Capture Kit
ADS7-V2EBZ

Latest Discussions

4 Years Ago
RE: ADL5569 with single end input and differential output to AD6674
6 Years Ago
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