AD9684
RECOMMENDED FOR NEW DESIGNS14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter
- Part Models
- 3
- 1ku List Price
- Starting From $349.25
Part Details
- LVDS digital outputs
- 1.1 W total power per channel at 500MSPS (default settings)
- SFDR = 85 dBc at 170MHz fIN (500MSPS)
- SNR = 68.6 dBFS at 170MHz fIN (500MSPS)
- ENOB = 10.9 bits at 170 MHz fIN
- DNL = ±0.5 LSB
- INL = ±2.5 LSB
- Noise Density = -153 dBFS/Hz at 500 MSPS
- 1.25V, 2.50 V and 3.3V supply operation
- No missing codes
- Internal analog-to-digital converter (ADC) voltage reference
- See data sheet for additional features
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.
Applications
- Communications
- Diversity multi-band, multi-mode digital receivers
3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE - General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- Radar
- Digital oscilloscopes
- High speed data acquisition systems
- DOCSIS CMTS upstream receive paths
- HFC digital reverse path receivers
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Device Drivers 1
Analog Dialogue 1
Rarely Asked Question Page 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9684BBPZ-500 | 196-Ball BGA (12mm x 12mm x 1.38mm w/ EP) | ||
| AD9684BBPZRL-500 | 196-Ball BGA (12mm x 12mm x 1.38mm w/ EP) | ||
| AD9684BBPZRL7-1500 | BGA THERM ENH W/ HEATSINK |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 0
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 1 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| Clock Generation Devices 1 | ||
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
| Digital Control VGAs 1 | ||
| ADA4961 | RECOMMENDED FOR NEW DESIGNS | Low Distortion, 3.2 GHz, RF DGA |
| Fully Differential Amplifiers 1 | ||
| ADL5565 | RECOMMENDED FOR NEW DESIGNS |
6 GHz Ultrahigh Dynamic Range Differential Amplifier |
| Internal Power Switch Buck Regulators 2 | ||
| ADP2164 | RECOMMENDED FOR NEW DESIGNS | 6.5V, 4 A, High Efficiency, Step-Down DC-to-DC Regulator |
| ADP2384 | RECOMMENDED FOR NEW DESIGNS | 20 V, 4 A, Synchronous Step-Down DC-to-DC Regulator |
| Positive Linear Regulators (LDO) 1 | ||
| ADP1741 | PRODUCTION | 2 A, Low VIN, Dropout, CMOS Linear Regulator |
Evaluation Kits
FPGA Based Data Capture Kit
AD9684 Evaluation Board