DS21552

新規設計には非推奨

3.3V DS21352および5V DS21552 T1シングルチップトランシーバ

データシート (Rev. 1)

Viewing:

製品の詳細

Complete DS1/ISDN-PRI/J1 transceiver functionality
Long and Short haul LIU
Crystal-less jitter attenuator
Generates DSX-1 and CSU line build-outs
HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation
Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
8.192MHz clock output locked to RCLK
Interleaving PCM Bus Operation
Per-channel loopback and idle code insertion
8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality
Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes
IEEE 1149.1 JTAG-Boundary Scan
Pin compatible with DS2152/54/354/554 SCTs
100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS

ドキュメント

データシート 2

DS21352-DS21552: 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers Data Sheet (Rev.1) 12/07/2000
- DS21352-DS21552: Errata Sheet
- DS21352-DS21552: Errata Sheet
- DS21352-DS21552: Errata Sheet

2849: 3.3V DS21352および5V DS21552 T1シングルチップトランシーバ Data Sheet 01/01/1900
- DS21352-DS21552: Errata Sheet
- DS21352-DS21552: Errata Sheet
- DS21352-DS21552: Errata Sheet

信頼性データ 1

DS21552 Reliability Data 01/12/2023

アプリケーション・ノート 4

T1/E1 Network Interface Design 11/27/2001

Using RCLK in a BITS/SSU Application 02/04/2002

DS2155 vs. DS21x5y: Software and Hardware Considerations 12/06/2001

DS21Q4x, DS215x, and DS21x5y Test Registers 03/29/2001

デザイン・ノート 20

マキシムT1/E1/J1トランシーバのT1/E1ループバック動作 03/16/2005

Elastic Store Operation 06/28/2004

Telecom Application Notes Index 08/10/2001

Provision Your DS2152 or DS2154 Hardware Design for the Next Generation Devices 03/29/2001

Interleaved Bus Operation 03/20/2006

T1/E1 Framer Initialization and Programming 08/10/2001

DS2151, DS2153 Device Identification 10/15/2001

DS21352/DS21552 versus DS2152 Single Chip Transceiver 08/10/2001

DS2151 Implementation of ANSI T1.231-1993 08/10/2001

HDLC Configuration of Framers and Transceivers 09/10/2002

NRZ Applications 08/30/2002

DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide 06/20/2002

DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32) 08/13/2002

D4 Framing and Signaling 08/10/2001

DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert 02/15/2002

Interfacing to the Fractional T1 and E1 05/04/2001

Programming and Controlling the FDL on DS2141A, DS2151 05/11/2001

J1 Japanese Standards 09/04/2002

Conversion Between T1 and E1 12/26/2001

Power-Fault Protection Layout 06/06/2003

技術記事 6

T3/E3/STS-1 LIU上でのリターンロスの測定 12/06/2005

Switching Frame Mode In Live T1 Systems 09/16/2003

DS21352/552, DS2151, DS2152, DS2141A, DS21Q42 Programming SLC-96 05/31/2001

Hitless Protection Switching with 1+1 Redundancy 06/07/2002

Selecting a T1/E1/J1 Single-Chip Transceiver 03/24/2004

T1/E1 and T3/E3 Transformer Selection Guide 10/15/2001

これは最新改訂バージョンのデータシートです。

ツールおよびシミュレーション

BSDLモデル・ファイル 1

ADSP-DS21552 BSDL Model

最新のディスカッション

ds21552に関するディスカッションはまだありません。意見を投稿しますか？

EngineerZone®でディスカッションを始める

最近表示した製品