AN-2065: Optimizing RF Performance of the AD9081 and AD9082

INTRODUCTION

The AD9081 and the AD9082 mixed signal front-end (MxFE^®) devices are high-performance, highly-integrated RF digital-to-analog converters (DAC) and RF analog-to-digital converters (ADC) used in many applications.

Both contain four 16-bit, 12 GSPS maximum sample rate DAC cores. The AD9081 contains four 12-bit, 4 GSPS rate ADC cores, while the AD9082 contains two 12-bit, 6 GSPS cores.

Both devices incorporate either a 16-lane, 24.75 Gbps JESD204C or a 15.5 Gbps JESD204B transceiver port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct-to-RF radio applications. Both parts feature an interpolator that can be bypassed and a decimator to achieve ultra-wideband capability along with low-latency loop back and frequency hopping modes targeted at phase array radar systems and electronic warfare jammer applications.

With careful balun selection and impedance matching, the AD9081 and AD9082 DACs and ADCs have a useable bandwidth of 7.5 GHz. Both the AD9081 and AD9082 can be driven directly with an external clock up to 12 GHz.

This application note can also be used to optimize the RF and clock front ends of the AD9988, AD9986, AD9207, AD9209 and AD9177. For more information on the key differences between these devices, refer to the UG-1578.

OVERVIEW

OPTIMIZING DAC/ADC/CLOCK PERFORMANCE AT HIGHER FREQUENCIES

Most RF interfaces are designed to be either 50 Ω single-ended or 100 Ω differential. However, this typically applies only at lower frequencies.

With the AD9081 and the AD9082 RF DACs, ADCs, and clocks operating up to 6 GHz or higher, the parasitic on the silicon die and the laminate package cause the input or output impedance to vary significantly over frequency.

The Smith chart in Figure 1 shows how the differential input impedance of the AD9081 ADC varies vs. frequency. Figure 1 shows that the differential input impedance of the AD9081 ADCs starts at 100 Ω at low frequencies, but then spirals around the Smith chart at higher frequencies. Figure 2 shows that the real part of the ADC input admittance ADC varies from 50 Ω to 250 Ω within the 0 to 8 GHz range.

All of the RF input/outputs (I/Os) for the AD9081 and AD9082 (ADC, DAC, and clock) can be modeled using the simple schematic shown in Figure 3.

The model starts with the expected 100 Ω differential resistor on the die. Each RF I/O includes some parasitic shunt capacitance (C_PAR) on the die that rotates the impedance down towards the lower left quadrant of the smith chart. The package traces (TL1, TL2) that route from the silicon die to the package BGA balls then rotate the impedance clockwise around the Smith chart, producing a Smith chart plot similar to that shown in Figure 1.

Because of this variation in impedance vs. frequency, it is necessary to design the system printed circuit board (PCB) carefully to obtain the optimum performance from the AD9081 in the particular band of interest.

The DAC output impedance and clock input impedance of the AD9081 and AD9082 have similar variations vs. frequency.

If a balun is used to convert differential signals to single-ended (or vice-versa), the balun impedance also varies over frequency, which also significantly impacts DAC, ADC, or clock performance. The variation of both the balun and ADC/DAC impedances vs. frequency produces a complex impedance matching problem, which makes it difficult to optimize performance over a wide frequency range without the use of circuit simulators.

Analog Devices, Inc. provides a Keysight Advanced Design System (ADS) circuit simulator archive that can be used to optimize PCB design and balun selection for the AD9081 and AD9082 DAC, ADC, and clock RF I/Os for a particular frequency band. The actual model information is contained in Touchstone format .sNp files that can also be used in other circuit simulators.

ADS ARCHIVE FOR AD9081 AND AD9082

The AD9081 and AD9082 RF models contained in the ADS archive (see Figure 4), which can be used to design a system board to achieve optimum performance over the particular band of interest. The ADS archive provides RF models for the RF DAC outputs, RF ADC inputs, and the clock input.

For all three RF interfaces, the ADS archive contains the following:

• S-parameter analysis that can be used to look at the input/output impedance of the 3 RF interfaces at the package BGA balls.
• A circuit analysis that can be used to simulate and optimize performance over frequency on the system board.

The actual DAC, ADC, and clock models for the AD9081 and AD9082 are a set of Touchstone .sNp files. For non-ADS users, these .sNp files are also included in the AD908x_Sparameter_ Models folder in the AD908x_RF_Models.zip file. The ADS schematics shown in this application note can be used to guide the setup and simulation of the AD9081 and AD9082 models in other circuit simulators.

The data folder, ADS Archive, also includes a folder named Balun s-parameters. The Balun s-parameters folder contains the following:

• S-parameters from the Min-Circuits website for their TCM1-83X+ (0.01 GHz to 8 GHz 1:1), TCM2-43X+ (0.01 GHz to 4 GHz 2:1), MTX2-143+ (5.5 GHz to 13.5 GHz 2:1), and NCR2-123+(4.7 GHz to 12 GHz 2:1) baluns.
• S-parameters from Murata for their 3.2 GHz to 6 GHz LDB184G6BAAE047 (1:1), LDB184G6BAAE048 (2:1), and LDB184G6BAAE049 (4:1) baluns.
• ADI measurement of Marki BALH-0009SMG (0.0005 GHz to 9 GHz 1:1) balun.
• S-parameters from Marki for their BAL-0416SMG (4 GHz to 16 GHz 2:1) balun.
• For non-ADS users, the baluns parameter folder can also be found in the AD908x_RF_Models.zip file.

The user can also use any set of balun s-parameters desired to simulate the AD9081 and AD9082 performance.

AD9081 AND AD9082 DAC MODELS

As shown in Figure 5, the package traces for the AD9081 DAC outputs are longer for DAC0 and DAC3 than for DAC1 and DAC2. At higher frequencies, the difference in length is significant, so the ADS archive contains separate models for DAC0 and DAC3, and DAC1 and DAC2.

DAC S-PARAMETER ANALYSIS

The DAC_S-parameter_Analysis schematic in the ADS archive can be used to look at the DAC output impedance of the AD9081 and AD9082 at the package BGA balls. Figure 8 shows what the schematic looks like. By enabling or disabling one of the two .s4p files, the user can select either the DAC0 and DAC3 outputs or the DAC1 and DAC2 outputs. Term2 in the schematic is the on-chip port where the DAC current sources are located. For the S-parameter analysis, Term2 is set to a high impedance. Term1 provides the simulated DAC output impedance at the package BGA balls.

For non-ADS users, the same .s4p files are included in the AD9081/2_RF_Models.zip file and can be used in any circuit simulator.

Figure 6 shows the results of running the DAC_S-parameter_ Analysis simulation. Figure 6 shows that like the AD9081 and AD9082 ADC input impedance, the DAC output impedance also varies significantly over frequency. Because of the shorter package traces, the DAC1 and DAC2 show less rotation around the Smith chart than DAC0 and DAC2. Figure 7 shows that, like the ADC input, the real part of the DAC output admittance is close to 100 Ω at low frequencies, dips down near 25 Ω around 3 GHz, and then rises above 100 Ω at higher frequencies.

DAC CIRCUIT ANALYSIS

The DAC_Circuit_Analysis schematic (see Figure 14) in the ADS archive can be used to simulate and optimize the DAC output power over a particular frequency range. For this circuit analysis, the ideal current sources are connected to the P1 and P2 of the DAC .s4p models.

The user selects the full-scale DAC output current (I_OUTFS), digital backoff (dBFS) and DAC operating frequency (f_DAC) settings. The user can then select either the DAC0 and DAC3 outputs or the DAC1 and DAC2 outputs by enabling or disabling the two .s4p files.

Figure 14 contains two simplified models for the PCB traces between the DAC outputs and the balun inputs. For the ideal model, the user selects the differential impedance of the PCB traces (Ω), and the electrical length of the traces (psec). This ideal analysis can be used to analyze the DAC performance with various PCB line impedances and lengths.

For the physical model of the PCB traces, the user defines the basic information of the PCB in the MSUB block (dielectric thickness, dielectric constant, and metal thickness) and then enters the particular information for the PCB traces in the MCLIN block (line width, line spacing, and line length). The physical model can be used to simulate the DAC performance with different PCB designs.

In practice, to get optimal agreement between simulated and measured DAC output power vs. frequency, ADI has found that it is necessary to perform an electromagnetic (EM) simulation of the PCB traces.

The user can select the S-parameters for the particular balun that they plan to use. As long as the traces and any coaxial connectors connected to the single-ended output of the balun are well-matched to 50 Ω, it is not necessary to include them in the DAC circuit analysis.

If the user plans to use the AD9081 and the AD9082 DACs to drive another differential component directly, the simplest way to run the DAC circuit analysis is to disable the balun .s3p file and enable the ideal 1:1 balun. It is then possible to modify the resistance of the Term1 to present any desired differential load impedance to the DAC.

The equations in the MeasEqn block shown in Figure 14 are used to calculate the power delivered to the 50 Ω load on the balun output.

The DAC represents a continuous time domain signal using discrete and uniform time intervals as shown in Figure 9. The zero-order hold or step response of the DAC results in a sin (x)/x frequency response is shown in Figure 10, where f_DAC is the frequency at which the DAC is operating.

Figure 11 shows that for f_DAC = 11.8 GHz, the Sin (x)/x roll off reduces DAC output power by approximately 4 dB at f_DAC/2 = 5.9 GHz. Figure 12 shows the simulated response of the AD9081 and AD9082 DACs with a typical balun, with and without the Sin(x)/x roll off.

It is possible to apply an inverse Sinc correction to the DAC outputs to partially compensate for the Sin (x)/x roll off (see Figure 13). The InvSinc function in the MeasEqn block shown in Figure 14 includes a curve fit equation for a typical inverse sinc filter. The InvSinc variable can be added to the simulated PTsinc calculation in the ADS data display. The AD9081 and AD9082 do not have an internal inverse sinc correction, but it can be applied at the system level using a FPGA or application-specific integrated circuit (ASIC). Further discussion of the InvSinc correction is included in the Optimizing AD9081 and AD9082 DAC Performance at Higher Frequencies section.

It is possible to extend the useable bandwidth of the AD9081 and AD9082 DACs into the 2^nd Nyquist zone above 6.0 GHz with the use of a low pass filter and amplifier. For more information, see the Optimizing AD9081 and AD9082 DAC Performance at Higher Frequencies section.

DAC MEASURED VS. SIMULATED OUTPUT POWER ON ADI EVALUATION BOARD

With accurate EM models of the system PCB and S-parameters for any balun that is used, it is possible to use the DAC_Circuit_Analysis schematic (see Figure 14) in the ADS archive to accurately predict DAC output power vs. frequency. Figure 15, Figure 16, and Figure 17 show the simulated and measured output power with three different commercially available SMT baluns. These simulations are done with full EM simulations of the PCB boards, which include the traces and the coax connectors on the balun output.

The agreement between measured and modeled P_OUT indicates that the AD9081 and AD9082 DAC models provide a useful tool for optimizing system board design for the desired DAC performance.

USING AD9081 AND AD9082 DAC MODELS TO OPTIMIZE SYSTEM PCB DESIGN

The output impedance of DAC0 and DAC3 is slightly different than DAC1 and DAC2 due to the longer traces in the AD9081 and AD9082 package. Figure 18 shows the simulated output power for the two different models using a TCM1-83X+ balun. Because of the longer traces, the DAC0 and DAC3 power rolls off at a lower frequency than DAC1 and DAC2.

Figure 19 shows the simulated POUT vs. frequency for the AD9081 and AD9082 DAC0/3 with ideal 1:1 and 2:1 baluns on the output. The 2:1 balun provides the higher output power at low frequencies where the DAC output impedance is close to 100 Ω. But in the 1 GHz to 5 GHz frequency range, where Figure 7 shows the DAC output impedance is closer to 50 Ω, the ideal 1:1 balun provides the highest output power. Note: The simulated curves shown in Figure 18 and Figure 19 include the sin (x)/x roll off due to the step response of the DAC.

In practice, ADI has found that 1:1 baluns like Marki BALH0009 and mini-circuits TCM1-83X+ balun provide the best wideband output power for the AD9081 and AD9082 DACs.

After the choice of the balun, the 2^nd most important feature of the PCB design is the differential traces that are used to connect the AD9081 and AD9082 DACs to the balun inputs. Figure 20 shows the simulated output power with ideal 100 Ω and 50 Ω differential pairs between the DAC outputs and the TCM1- 83X+ balun. Because DAC output impedance is closer to 50 Ω in the 2 GHz to 4 GHz range, the 50 Ω differential PCB trace yields the best performance in that frequency range. ADI used 50 Ω differential pairs on the AD9081 and AD9082 PCBs to route the DAC outputs to the balun inputs.

In addition to the impedance of the PCB traces between the DAC and the balun, the length of those traces also acts as a tuning element between the output impedance of the DAC and the input impedance of the balun, which both vary widely over the frequency. Figure 21 shows that for the TCM1-83X+ balun, a shorter 50 Ω differential pair line length provides the best 3 dB bandwidth.

The final tuning element to optimize the AD9081 and AD9082 DAC output power is the option to add some small shunt tuning capacitors at the input ports of the balun. As shown in Figure 22, the simulations indicate that using a small capacitor at the input of the BALH-0009 improves DAC performance up near 4.0 GHz.

However, Figure 23 shows that for the TCM1-83X+, additional capacitance at the balun input causes a small reduction in 3 dB bandwidth. EM simulations showed that by moving the GND plane for the TCM1-83X+ balun from Layer 2 to Layer 3 of the PCB, it is possible to reduce the parasitic capacitance of the balun pads and improve the high frequency response of the DAC.

OPTIMIZING AD9081 AND AD9082 DAC PERFORMANCE AT HIGHER FREQUENCIES

As mentioned in the DAC Circuit Analysis section, the Sin (x)/x roll off of the AD9081 and AD9082 DACs can be corrected by applying an inverse sinc filter function using an external FPGA or ASIC. By adding the InvSinc variable to the PTdBm variable in the DAC_Circuit_Analysis data set, it is possible to simulate the expected P_OUT with the inverse sinc filter applied.

Figure 24 shows the measured AD9081 and AD9082 DAC output power vs. frequency with the BALH-0009 balun. The inverse sinc correction improves the 3 dB bandwidth from 4 GHz to 5 GHz. Figure 25 shows that applying the inverse sinc function to the measured P_OUT with the LDB184G6BAAE048 Murata 2:1 balun provides a relatively flat response from 2 GHz to 6 GHz.

Measurements are also performed to show that it is possible to operate the AD9081 and AD9082 DACs in the 2^nd Nyquist zone (above 5.9 GHz when f_DAC = 11.8 GHz). Figure 27 shows the measurement setup that is used. The Murata 3.2 GHz to 6.0 GHz 2:1 balun is used as it provided the flattest frequency response in the 5 GHz to 6 GHz frequency range. A Mini-Circuits high pass filter rejected all the DAC output power below 6.3 GHz. Finally, an HMC3653 gain block is used to amplify the DAC output signal above 6.3 GHz.

The measured and simulated AD9081 and AD9082 DAC output power in the 2^nd Nyquist zone is shown in Figure 26. The signal chain in Figure 27 shows greater than 0 dBm from 6.4 GHz to 8.3 GHz. The rough shape of the simulated and measured frequency response matches very well. The different peaks and valleys in the measured and simulated data are likely due to the cable lengths that are used to connect the various evaluation boards. Those cable lengths are not included in the simulation.

Figure 28 shows that the signal chain provides EVM = −52.9 dBC for 256 QAM signal at 7.5 GHz with 100 MHz 5G FR2 vector.

DAC SUMMARY

Because the output impedance of the AD9081 and AD9082 DACs vary significantly over frequency, it is necessary to use the simulation tools for balun selection and PCB design to optimize the performance over a particular band of interest. The DAC_Circuit_Analysis schematic (see Figure 14) in the ADS archive can be used to perform this task.

The key design parameters to optimize the DAC performance are the following:

• Balun selection.
• Impedance of PCB traces between the DAC output and the balun input.
• Length of PCB traces between the DAC output and the balun input.
• Shunt capacitance at the balun input.

In addition to the items in the previous list, take care that any PCB traces or coax connectors on the balun output are also well-matched to 50 Ω.

To achieve good correlation between simulated and measured AD9081 and AD9082 DAC output power vs. frequency, it is necessary to do a full-EM simulation of all the PCB traces to consider all of their parasitic (for example, mounting pads, vias, and coax connectors).

With the available models, correct balun selection, and careful optimization of the PCB, it is possible to achieve 3 dB bandwidth up to 4.5 GHz. Applying an external inverse sinc correction boosts 3 dB bandwidth to 5.25 GHz. Operating the AD9081 and AD9082 DACs in the 2^nd Nyquist zone, it is possible to achieve usable bandwidth as high as 7.5 GHz.

AD9081 AND AD9082 ADC MODELS

The AD9081 contains four 12-bit, 4 GSPS rate ADC cores, while the AD9082 contains two 12-bit, 6 GSPS cores. Because of this difference, the two ADCs have different input impedances and models.

ADC S-PARAMETER ANALYSIS

The ADC_S-parameter_Analysis schematic (see Figure 31) in the ADS archive can be used to look at the ADC input impedance of the AD9081 and AD9082 at the package BGA balls. By enabling or disabling one of the two .s3p files, the user can select either the AD9081 or the AD9082 ADCs. Port 3 of the .s3p file is the high impedance node at the input of the ADC sampler; therefore, for the S-parameter analysis, that port is terminated in a high impedance.

For non-ADS users, the same .s3p files are included in the AD9081/2_RF_Models.zip file and can be used in any circuit simulator.

Figure 29 shows the results of running the ADC S-parameter analysis simulation. The AD9081 curve matches up with Figure 1, but because the AD9082 ADC front end has higher on-chip parasitic, its input impedance varies a bit more over frequency than the AD9081. Figure 30 shows that the real part of the ADC input admittance is close to 100 Ω at low frequencies, dips down near 50 Ω between 2 GHz to 4 GHz, and then increases above 4 GHz.

ADC CIRCUIT ANALYSIS

The ADC_Circuit_Analysis schematic (see Figure 32) in the ADS archive can be used to simulate and optimize the ADC performance over a particular frequency range. The user selects the desired input power (dBm), then, like the S-parameter schematic, by enabling or disabling the two .s3p files, the user can select either the AD9081 or the AD9082 ADC.

Port 3 of the .s3p model is the input to the ADC sampler, so it is terminated in a high impedance.

Next, the user can select the S-parameters for the particular balun that they plan to use.

Figure 32 contains two simplified models for the PCB traces between the balun outputs and the ADC inputs. For the ideal model, the user selects the differential impedance of the PCB traces (Ω), and the electrical length of the traces (psec). This ideal analysis can be used to analyze ADC performance with various PCB line impedances and lengths.

For the physical model of the PCB traces, the user defines the basic information of their PCB in the MSUB block (dielectric thickness, dielectric constant, and metal thickness) and then enters the particular information for the PCB traces in the MCLIN block (line width, line spacing, and line length). The physical analysis can be used to simulate ADC performance with different PCB designs.

In practice, to get good agreement between simulated and measured ADC frequency response, ADI has found that it is necessary to perform an EM simulation of the PCB traces.

As long as the traces and any coaxial connectors connected to the single-ended input of the balun are well-matched to 50 Ω, it is not necessary to include them in the AC simulation.

If the user plans to directly drive the AD9081 and AD9082 ADCs with a differential signal, the simplest way to run the circuit analysis is to disable the balun .s3p file and enable the ideal 1:1 balun. It is then possible to modify the resistance of Port 2 to present any desired differential source impedance to the ADC.

The equations in the MeasEqn block shown in Figure 32 are used to sense the voltage delivered to the ADC sampler and convert it into a dBFS value based on full-scale ADC input voltage of 0.7375 V peak (1.475 Vp-p). For debugging purposes, the ADC sampling voltage is also converted to power (dBm) value assuming 100 Ω load impedance.

ADC MEASURED VS. SIMULATED FREQUENCY RESPONSE ON ADI EVALUATION BOARD

With accurate EM models of the system PCB and s-parameters for any balun that is used, it is possible to use the ADC_Circuit_Analysis schematic shown in Figure 32 to accurately predict the frequency response of the AD9081 and AD9082 ADCs. Figure 33 and Figure 34 show the simulated and measured response of the AD9081 ADC with the TCM1- 83X+ and BALH-0009 baluns. These simulations are done with full-EM simulations of the PCBs, including the traces and coax connectors on the balun output.

The good agreement between measured and modeled P_OUT indicates that the AD9081 and AD9082 ADC models provide a useful tool to optimize the system board design for the desired ADC performance.

USING AD9081 AND AD9082 ADC MODELS TO OPTIMIZE SYSTEM PERFORMANCE

The input impedances of the AD9081 and AD9082 ADCs are slightly different. Figure 35 shows the simulated frequency response for the two different models using an TCM1-83X+ balun. The AD9082 rolls off a bit faster at higher frequencies than the AD9081 due to its slightly higher parasitic.

Figure 36 shows the simulated ADC response for the AD9081 with ideal 1:1 and 2:1 baluns on its input. As per Figure 30, the 2:1 balun provides best ADC response at lower and higher frequencies where the ADC input impedance is close to 100 Ω. But in the 2 GHz to 4 GHz frequency range where the ADC impedance is closer to 50 Ω, the ideal 1:1 balun provides the higher signal to the ADC inputs.

Based on the simulations with ideal baluns in Figure 36, it appears that a 2:1 balun provides the best bandwidth for the AD9081 and AD9082 ADCs. However, balun impedances vary significantly over frequency, and the PCB trace length between the balun outputs and the ADC inputs also provides an impedance transformation. Based on simulations and measurements, it is determined that the optimum ADC bandwidth is obtained with a 1:1 balun, such as the TCM1-83X+ and 100 Ω differential PCB traces.

After the choice of the balun, the 2^nd most important feature of the PCB design is the differential traces that are used to connect the balun to the ADC inputs. Figure 37 shows the simulated ADC response with ideal 100 Ω and 50 Ω differential pairs between the ADC inputs and the TCM1-83X+ balun. Figure 37 shows that the 100 Ω differential pairs give the best overall performance. This is unexpected considering the TCM1-83X+ is a 1:1 balun. The balun output impedance varies significantly over frequency, as does the AD9081 ADC input impedance. Therefore, the interaction between those impedances and the PCB trace impedance and length is a complex impedance matching problem that can only be solved by using a circuit simulator.

In addition to the impedance of the PCB braces between the balun and the ADC, the length of those traces also acts as a tuning element between the output impedance of the balun and the input impedance of the ADC. Figure 38 shows that for the TCM1-83X+ balun, a shorter 100 Ω differential pair line length provides the best 3 dB bandwidth.

The final tuning element to optimize the AD9081 and AD9082 ADC response is the option to add small shunt tuning capacitors at the output ports of the balun. Figure 39 shows that adding shunt capacitors at the TCM1-83X+ balun inputs degrade the performance at higher frequency. EM simulations showed that by moving the GND plane for the balun from Layer 2 to Layer 3 of the PCB, it is possible to reduce the parasitic capacitance of the balun pads and improve the high frequency response of the ADC.

OPTIMIZING AD9081 AND AD9082 ADC PERFORMANCE AT HIGHER FREQUENCIES

As shown in Figure 33, the AD9081 ADC model, along with EM simulations of the AD9081 and AD9082 evaluation boards, provides a simulated and measured ADC response vs. frequency with a 3 dB bandwidth near 7 GHz with the TCM1- 83X+ balun. To show the ADC performance above 7 GHz, ADC has redesigned the PCB that uses the TCM1-83X+.

The design changes to the Rev B PCB design removes some extra optional SMT components between the balun outputs and the ADC inputs and used the ADC circuit analysis schematic as shown in Figure 32 to adjust the length of the 100 Ω differential pairs connecting the balun to the ADC. Figure 40 shows that these design tweaks provided measured and simulated AD9082 3 dB bandwidth > 8.5 GHz.

ADC SUMMARY

Because the input impedance of the AD9081 and AD9082 ADCs vary significantly over frequency, it is necessary to use the simulation tools for balun selection and PCB design to optimize the ADC response over a particular band of interest. The ADC_Circuit_Analysis schematic (see Figure 32) in the ADS archive can be used to perform this task.

The key design parameters to optimize the ADC performance are the following:

• Balun selection.
• Impedance of PCB traces between the balun output and the ADC input.
• Length of PCB traces between the balun output and the ADC input.
• Shunt capacitance at the balun output.

In addition to the items in the previous list, take care that any PCB traces or coax connectors on the balun input are also well-matched to 50 Ω.

To achieve good correlation between simulated and measured AD9081 and AD9082 ADC frequency response, it is necessary to do a full-EM simulation of all the PCB traces to consider all of their parasitic (mounting pads, vias, and coax connectors).

With proper balun selection and careful design of the PCB, it is possible to achieve 3 dB bandwidth greater than 7.5 GHz for the AD9081 and AD9082 ADCs.

AD9081 AND AD9082 CLOCK MODELS

The AD9081 and AD9082 can be driven with an external clock signal as high as 12 GHz. The ADS archive provides a model to help optimize the PCB design to maximize the voltage delivered to the clock inputs in a particular frequency range.

CLOCK S-PARAMETER ANALYSIS

The clock s-parameter analysis schematic in the ADS archive (see Figure 43) can be used to look at the clock input impedance of the AD9081 and AD9082 at the package BGA balls. TERM2 is the high impedance node at the clock input buffer. Therefore, for the S-parameter analysis, TERM2 is terminated in a 1 MΩ resistor.

For non-ADS users, the same .s4p file is included in the AD9081/2_RF_Models.zip file and can be used in any circuit simulator.

Figure 41 and Figure 42 show the results of running the CLK_S-parameter_Analysis simulation. Figure 42 shows that the real part of the clock input admittance is close to 100 Ω at low frequencies, dips down near 50 Ω between 3 GHz to 6 GHz, and then increases to 400 Ω at 12 GHz.

CLOCK CIRCUIT ANALYSIS

The CLK_Circuit_Analysis schematic (see Figure 44) in the ADS archive can be used to simulate and optimize the clock performance over a particular frequency range.

Port 3 and Port 4 of the .s4p model are the inputs to the clock buffer and both are terminated in a high impedance. For optimum clock performance, the voltage delivered across these two ports must be > 1.0 Vp-p.

In Figure 44, the user can select different balun .s3p files to use in the circuit simulation.

The schematic shown in Figure 44 also contains two simplified models for the PCB traces between the balun outputs and the clock inputs. For the ideal model, the user selects the differential impedance of the PCB traces (Ω), and the electrical length of the traces (psec). This ideal analysis can be used to analyze clock performance with various PCB line impedances and lengths.

For the physical model of the PCB traces, the user defines the basic information of the PCB in the MSUB block of the schematic shown in Figure 44 (dielectric thickness, dielectric constant, and metal thickness), and then enters the particular information for the PCB traces in the MCLIN block (line width, line spacing, and line length). The physical model can be used to simulate clock performance with different PCB designs.

If the user plans to directly drive the AD9081 and AD9082 clock with a differential signal, the simplest way to run the AC analysis is to disable the balun .s3p file and enable the ideal 1:1 balun. It is then possible to modify the resistance of the Port 2 impedance to present any desired differential source impedance to the clock.

The equations in the MeasEqn block in the ADS schematic shown in Figure 44 are used to sense the peak-to-peak voltage delivered to the clock buffer. For debugging purposes, the clock voltage is also converted to power (dBm) value assuming 100 Ω load impedance.

USING AD9081 AND AD9082 CLOCK MODELS TO OPTIMIZE SYSTEM PERFORMANCE

Figure 45 shows the simulated clock response for the AD9081 and AD9082 with ideal 1:1 and 2:1 baluns on its input. As seen in Figure 42, the clock input impedance varies significantly vs. frequency. Figure 45 shows that the 2:1 balun provides the best clock response at lower and higher frequencies, but in the 2 GHz to 6 GHz frequency range, where Figure 42 shows the clock impedance is closer to 50 Ω, the ideal 1:1 balun provides the highest voltage to the clock inputs.

To get the best performance at the maximum clock rate of 12 GHz, the AD9081 and AD9082 is recommended to use 2:1 baluns. Figure 46 provides the simulated V_CLK voltage for the Marki BAL-0416SMG (4 GHz to 16 GHz 2:1), Mini-Circuits MTX2- 143+ (5.5 GHz to 13.5 GHz 2:1) and NCR2-123+ (4.7 GHz to 12 GHz 2:1) baluns.

After the choice of balun, the 2^nd most important feature of the PCB design is the differential traces that are used to connect the balun to the clock inputs. Figure 47 shows that the 100 Ω differential pairs deliver a larger voltage swing to the clock inputs than a 50 Ω PCB trace.

In addition to the impedance of the PCB braces between the balun and the clock inputs, the length of those traces also acts as a tuning element between the output impedance of the balun and the input impedance of the clock. Figure 48 shows that for the MTX2-143+ balun, the length of the 100 Ω differential pair connecting the balun to the clock input causes significant peaks and valleys in the voltage that is actually delivered to the clock buffer. Consequently, the length of this PCB trace must be adjusted to reach a maximum at the particular clock frequency of interest.

For high RF clock frequency generation beyond 4.5 GHz, a wideband synthesizer IC such as the ADF5610 or the ADF4372 can be considered. These ICs have fundamental voltage-controlled oscillator (VCO) modes extending up to 7.3 GHz and 8.0 GHz, respectively, with an internal clock doubler used to synthesize output frequencies beyond the fundamental VCO limit.

Figure 50 shows a suggested solution to drive the AD9081 and AD9082 clock inputs at 12 GHz. The ADF4372 doubler output is adjusted to provide −4 dBm of output power. The Mini-Circuits NCR2-123+ balun is used to convert the ADF4372 differential outputs to 50 Ω single ended, which is then amplified by the HMC3653 gain block and filtered by the Knowles B096QC2S 8 GHz to 12 GHz band pass filter. Finally, a second NCR2-123+ balun converts the single-ended output of the filter to a differential signal to drive the AD9081 and AD9082 clock inputs. The optional 2 dB pads are used to reduce voltage standing-wave ratio (VSWR) interactions between the various components.

Simulations show that this signal chain provides the required 1.0 Vp-p voltage at the AD9081 and AD9082 clock input buffers (see Figure 49).

CLOCK SUMMARY

Because the input impedance of the AD9081 and AD9082 clock varies significantly over frequency, it is necessary to use simulation tools for balun selection and PCB design to optimize performance over a particular band of interest. The clock circuit analysis schematic shown in Figure 43 can be used to perform this task.

The key design parameters to optimize the voltage that is delivered to the clock input buffer are the following:

• Balun selection.
• Impedance of PCB traces between the balun output and the clock input.
• Length of the PCB traces between the balun output and the clock input.

In addition to the items in the previous list, take care that any PCB traces or coax connectors on the balun input are also well-matched to 50 Ω.

To accurately predict the clock frequency response, it is necessary to do a full-EM simulation of the clock PCB traces to account for all of the parasitics (mounting pads, vias, and coax connectors).