MAX9388
PRODUCTIONDifferential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
Industry's First 2.5GHz LVECL/LVPECL Multiplexers
- Part Models
- 2
- 1ku List Price
- Starting From $7.76
Part Details
- 318ps (typ) Propagation Delay
- >2.7GHz Toggle Frequency
- 0.3ps(RMS) Random Jitter
- <14ps (max) at +25°C Output-to-Output Skew (MAX9387)
- -2.375V to -5.5V Supplies for Differential LVECL/ECL
- +2.375V to +5.5V Supplies for Differential LVPECL/PECL
- Outputs Low for Open Inputs
- Dual Output Buffers (MAX9387)
- Pin Compatible with MC100EP57 (MAX9388EUP)
- >2kV ESD Protection (Human Body Model)
The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, low-jitter ECL/PECL multiplexers (muxes) with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57.
Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output VBB, nominally VCC - 1.425V. The select inputs accept signals between VCC and VEE. Internal pulldowns to VEE ensure a low-default condition if the select inputs are left open.
The differential inputs D_, D_ -bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias and clamping circuits that ensure low-default output states when the inputs are left open. The MAX9386/MAX9387/MAX9388 operate with a wide supply range |VCC - VEE| of 2.375V to 5.5V. The MAX9386/MAX9388 are offered in 20-pin TSSOP and QSOP packages. The MAX9387 is offered in 24-pin TSSOP and QSOP packages.
Applications
- Central Office Backplane Clock Distribution
- DSLAM/DLC
- High-Speed Telecom and Datacom Applications
Documentation
Data Sheet 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| MAX9388EUP+ | Thin Shrink Small-Outline Package | ||
| MAX9388EUP+T | Thin Shrink Small-Outline Package |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Generation and Distribution 1 | ||
| MAX9389 | LAST TIME BUY | Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers |
| Product 2 | ||
| MAX9380 | Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer | |
| MAX9387 | Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers | |
Tools & Simulations
IBIS Model 1
Latest Discussions
No discussions on max9388 yet. Have something to say?
Start a Discussion on EngineerZone®