DS33R41
Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
Greatly Simplifies the Design of Applications for Transporting Ethernet Packets Over Up to Four T1 or E1 Lines
Part Details
- 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
- Layer 1 Inverse Multiplexing Over Four T1/E1/J1 Lines Through the Integrated Framers and LIUs
- Supports Up to 7.75ms Differential Delay
- Aggregate Bandwidth from Up to Four T1/E1/J1 Links
- T1/E1 Signaling Capability for OAM
- HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill
- CIR Controller Provides Fractional Allocations in 512kbps Increments
- Programmable BERTs
- External 16MB, 100MHz SDRAM Buffering
- Parallel Microprocessor Interface
- 1.8V, 3.3V Power Supplies
- IEEE 1149.1 JTAG Support
The DS33R41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four interleaved T1/E1/J1 lines using a robust, balanced, and programmable inverse multiplexing. Four integrated T1/E1/J1 transceivers provide framing and line interfacing functionality.
The device performs store-and-forward of packets with full wire-speed transport capability. The built-in committed information rate (CIR) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps.
Applications
- Bonded Transparent LAN Service
- Ethernet Delivery Over T1/E1/J1
- LAN Extension
Documentation
Data Sheet 1
Reliability Data 1
Technical Articles 1
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Product 5 | ||
| DS33R11 | Ethernet Mapper with Integrated T1/E1/J1 Transceiver | |
| DS33Z41 | Quad IMUX Ethernet Mapper | |
| DS33Z11 | Ethernet Mapper | |
| DS33Z44 | Quad Ethernet Mapper | |
| DS21458 | Quad T1/E1/J1 Transceivers |
Tools & Simulations
IBIS Model 1
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