ADDI7013

Obsolete

Dual-Channel CCD Signal Processor with Precision Timing Core

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Part Details

  • CDS or SHA (CDS bypass) with 7 gain settings
  • 0 dB to 36 dB, 10-bit variable gain amplifier (VGA)
  • 16-bit, 75 MSPS analog-to-digital converter (ADC)
  • Precision Timing core with 210 ps resolution at 75 MHz
  • 8 independent H-clock phases with programmable drive strength (3.6V maximum swing)
  • Differential analog inputs
  • 4 general-purpose outputs (GPO)
  • On-chip sync generator with external sync input
  • Reduced-range LVDS outputs with single clock lane
  • 6 mm × 6 mm CSP_BGA package with 0.5 mm pitch
ADDI7013
Dual-Channel CCD Signal Processor with Precision Timing Core
ADDI7013 Functional Block Diagram ADDI7013 Pin Configuration
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