AD9690
RECOMMENDED FOR NEW DESIGNS14-Bit, 500 MSPS / 1 GSPS JESD204B, Analog-to-Digital Converter
- Part Models
- 4
- 1ku List Price
- Starting From $174.62
Part Details
- JESD204B (Subclass 1) coded serial digital outputs
- 2.0 W total power at 1 GSPS (default settings)
- 1.5 W total power at 500 MSPS (default settings)
- SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz
- SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 985 MHz
- ENOB = 10.8 bits at 10 MHz
- DNL = ±0.5 LSB
- INL = ±2.5 LSB
- Noise density = −154 dBFS/Hz at 1 GSPS
- 1.25 V, 2.5 V, and 3.3 V dc supply operation
- No missing codes
- Internal ADC voltage reference
- Flexible input range
- AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
- AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
- Programmable termination impedance
- 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
- 2 GHz usable analog input full power bandwidth
- Amplitude detect bits for efficient AGC implementation
- 2 integrated wideband digital processors
- 12-bit NCO, up to 4 cascaded half-band filters
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9690 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. The ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters.
In addition to the DDC blocks, the AD9690 has several functions that simplify the automatic gain control (AGC) function in the communications receiver.
The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane con-figurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9690 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
p>The AD9690 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product may be protected by one or more U.S. or international patents.
Product Highlights
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Two integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm 64-lead LFCSP.
Applications
- Communications
- Multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Instrumentation
- Radars
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Documentation
Data Sheet 1
FPGA Interoperability Reports 2
Analog Dialogue 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9690BCPZ-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9690BCPZ-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9690BCPZRL7-1000 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9690BCPZRL7-500 | 64-Lead LFCSP (9mm x 9mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Mar 14, 2017 - 16_0274 AD9690-1000 and AD9690-500 Die Revision and Data Sheet Change |
||
| AD9690BCPZ-1000 | PRODUCTION | |
| AD9690BCPZ-500 | PRODUCTION | |
| AD9690BCPZRL7-1000 | PRODUCTION | |
| AD9690BCPZRL7-500 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| Clock Generation Devices 4 | ||
| LTC6951 | LAST TIME BUY | Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
Tools & Simulations
IBIS Model 1
AD9690 AMI Model, Rev. 1.2
Open ToolADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolEvaluation Kits
AD9680/AD9234/AD9690 Evaluation Board