LTC6952
LAST TIME BUYUltralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support
- Part Models
- 2
- 1ku List Price
- Starting From $19.54
Part Details
- JESD204B/C, Subclass 1 SYSREF Signal Generation
- Low Noise Integer-N PLL
- Additive Output Jitter < 6fsRMS
- (Integration BW = 12kHz to 20MHz, f = 4.5GHz)
- Additive Output Jitter 65fsRMS (ADC SNR Method)
- EZSync™, ParallelSync™ Multichip Synchronization
- –229dBc/Hz Normalized In-Band Phase Noise Floor
- –281dBc/Hz Normalized In-Band 1/f Noise
- Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays
- Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal
- Reference Input Frequency up to 500MHz
- LTC6952Wizard™ Software Design Tool Support
- –40ºC to 125°C Operating Junction Temperature Range
The LTC6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider. The LTC6952’s eleven outputs can be configured as up to five JESD204B/C subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply eleven general purpose clock outputs for non-JESD204B/C applications. Each output has its own individually programmable frequency divider and output driver. All outputs can also be synchronized and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays.
For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the EZSync or ParallelSync synchronization protocols.
Applications
- High Performance Data Converter Clocking
- Wireless Infrastructure
- Test and Measurement
Documentation
Data Sheet 1
User Guide 4
Application Note 1
Product Selection Guide 1
Analog Dialogue 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
---|---|---|---|
LTC6952IUKG#PBF | 52-Lead QFN (7mm x 8mm x 0.75mm w/ EP) | ||
LTC6952IUKG#TRPBF | 52-Lead QFN (7mm x 8mm x 0.75mm w/ EP) |
Part Models | Product Lifecycle | PCN |
---|---|---|
Mar 20, 2024 - 23_0089 Obsolescence of Tower Fab3 (JAZZ-3) SBC35 Process |
||
LTC6952IUKG#PBF | LAST TIME BUY | |
LTC6952IUKG#TRPBF | LAST TIME BUY |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
Parts | Product Life Cycle | Description |
---|---|---|
Clock Distribution Devices 2 | ||
LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
High Speed Comparators (<100ns Propagation Delay) 1 | ||
LTC6957 | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter | |
Integer-N PLL 1 | ||
ADF4002 | RECOMMENDED FOR NEW DESIGNS | Phase Detector / PLL Frequency Synthesizer |
Parts | Product Life Cycle | Description |
---|---|---|
HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
Tools & Simulations
Linduino 3
Design Tool 1
IBIS Model 1
LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.
Linduino is Analog Devices’ Arduino compatible system for developing and distributing firmware libraries and example code for our integrated circuits. Each Linduino-supported product includes an example main program, defined in the LTSketchbook/Part Number folder and driver code, defined in the LTSketchbook/libraries folder.
Linduino code repository on GitHub and instructions on how to use the code.