AD7542

不推荐用于新设计

精密12位CMOS乘法电流输出DAC，采用4位总线

数据手册 (Rev. A) 产品选型表

产品模型: 12

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产品详情

分辨率：12位
非线性度：±1/2 LSB T_min 至 T_max
低增益漂移：2 ppm/°C（典型值），5 ppm/°C（最大值）
微处理器兼容
完全四象限乘法

快速接口定时
低功耗：40 mW（最大值）
低成本
小尺寸：16引脚DIP和20引脚表贴封装
无闩锁现象（无需肖特基二极管保护）

参考资料

数据手册 1

AD7542: CMOS µP-Compatible 12-Bit DAC Scanned Data Sheet (Rev.A) 01/21/1980

应用笔记 3

AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V and 12V Systems 01/01/2000

AN-328: Generate 4 Channels of Analog Output Using AD7542 12-Bit DAC and Control the Lot with Only 2 Wires 09/30/2002

AN-319: Simple Interface Between D/A Converter and Microcomputer Leads to Programmable Sine-Wave Oscillators 01/01/2000

ADI 始终高度重视提供符合最高质量和可靠性水平的产品。我们通过将质量和可靠性检查纳入产品和工艺设计的各个范围以及制造过程来实现这一目标。出货产品的“零缺陷”始终是我们的目标。查看我们的质量和可靠性计划和认证以了解更多信息。

产品型号	引脚/封装图-中文版	文档	CAD 符号，脚注和 3D模型
AD7542AQ	24-Lead CerDIP (Narrow 0.3 Inch)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542BQ	24-Lead CerDIP (Narrow 0.3 Inch)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542GBQ	24-Lead CerDIP (Narrow 0.3 Inch)	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542GKNZ	16-Lead PDIP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542GTQ/883B	16-Lead CerDIP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542JNZ	16-Lead PDIP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542JPZ	20-Lead Flatpack	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542KNZ	16-Lead PDIP	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542KPZ	20-Lead Flatpack	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542KPZ-REEL	20-Lead Flatpack	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542KRZ	16-Lead SOIC Wide	Material Declaration Reliablity Data	Ultra Librarian SamacSys
AD7542TQ/883B	16-Lead CerDIP	Material Declaration Reliablity Data	Ultra Librarian SamacSys

产品型号	产品生命周期	PCN

11月 7, 2012 - 12_0199 Qualification of New Conductive Silver-Filled Glass Die Attach Adhesive for Cerdip and Ceramic Flatpack (Cerpack) Packages.
		PCN12_0199_Form Material_Report Qualification Report Summary Datasheet Specification Comparison
AD7542AQ
AD7542BQ
AD7542GBQ
AD7542GTQ/883B
AD7542TQ/883B
11月 9, 2011 - 11_0050 Transfer of ADI Hermetics Assembly location from Paranaque, Manila to General Trias, Cavite Philippines
		PCN11_0050_Form Material_Report
AD7542AQ
AD7542BQ
AD7542GBQ
AD7542GTQ/883B
AD7542TQ/883B
11月 9, 2011 - 11_0182 Test Site Transfer from Analog Devices Philippines Inc in Paranaque to Analog Devices General Trias in Cavite, Philippines
		PCN11_0182_Form Material_Report
AD7542AQ
AD7542BQ
AD7542GBQ
AD7542GTQ/883B
AD7542TQ/883B
2月 8, 2010 - 04_0080 Qualification of the 8" C6 and Q Wafer Fab Processes at Analog Devices, Limerick, Ireland.
		PCN04_0080_Form Material_Report Reliability Report Reliability Report
AD7542AQ
AD7542BQ
AD7542GBQ
AD7542GKNZ	量产
AD7542JNZ	量产
AD7542JPZ	量产
AD7542KNZ	量产
AD7542KPZ	量产
AD7542KRZ	量产
AD7542TQ/883B
8月 19, 2009 - 07_0024 Package Material Changes for SOT23, MiniSO, MQFP, PDIP, PLCC, SOIC (narrow and wide body), SSOP, TSSOP and TSSOP exposed pad
		Material_Report Material_Report Parts List PCN07_0024_Form Qual Data
AD7542GKNZ	量产
AD7542JNZ	量产
AD7542KNZ	量产
4月 9, 2018 - 16_0026 Qualify TeamQuest Technology, Inc. for Burn-in and Life Test of Military and Aerospace Devices
		PCN16_0026_Form Material_Report Qualification Results Summary
AD7542GTQ/883B
AD7542TQ/883B
2月 1, 2010 - 10_0020 Test Solutions Services, Inc.(TSSI) as Subcontractor Burn-in Facility.
		Material_Report PCN10_0020_Form Qual Plan
AD7542GTQ/883B
AD7542TQ/883B
3月 29, 2021 - 21_0033 Assembly Site Transfer for 14/16L 300_MIL PDIP to Cirtek
		PCN21_0033_Form Material_Report Detailed Change Description Qualification Results Summary
AD7542JNZ	量产
AD7542KNZ	量产
8月 4, 2010 - 10_0117 Halogen Free Material Change for SOIC_W Products at Carsem
		PCN10_0117_Form Material_Report Reliability Report
AD7542KRZ	量产	PCN10_0117_Form Material_Report Reliability Report

这是最新版本的数据手册

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精密DAC误差预算工具

精密DAC误差预算工具是一种Web应用程序，用于计算精密DAC信号链的直流精度。它可显示整个信号链中的静态误差状况，以快速评估设计利弊。可计算由基准电压源、运算放大器和精密DAC引起的直流误差。

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