製品概要
機能と利点
- Simple power connection using USB connection and on-board LDO voltage regulators
- LDOs can be bypassed for power measurements
- AC-coupled differential SMA connectors
- SMA connectors for
2 reference Inputs
6 clock outputs
1 VCXO output - Microsoft Windows®–based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital input/output and diagnostic signals via input/output header (4 GPIOs)
- Status LEDs for diagnostic signals
- USB computer interface
製品概要
The HMC7044 meets the requirements of multi-carrier GSM and LTE base-station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.
The EK1HMC7044LP10B evaluation board is a compact, easy-to-use platform for evaluating all the features of the HMC7044. A 122.88 MHz VCXO is mounted on the evaluation board to provide a complete solution. All inputs and outputs are configured as differential on the evaluation board.
Full specifications on the HMC7044 are available in the product data sheet, which should be consulted in conjunction with this user guide when working with the evaluation board.
マーケット&テクノロジー
対象となる製品
関連資料
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ADIsimCLK 設計・評価 ソフトウェア2015/05/12
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UG-826: Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner (Rev. 0)2015/09/28PDF855 K
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Assembly Drawing2016/04/27PDF
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Bill of Materials2016/04/27XLS
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FAB Drawing2016/04/27PDF
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Layout2016/04/27ZIP
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Schematic2016/04/27PDF
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Assembly Drawing2015/09/28PDF
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Bill of Materials2015/09/28XLS
-
FAB Drawing2015/09/28PDF
-
Layout2015/09/28ZIP
-
Schematic2015/09/28PDF