CN0571

Figure 3 shows a simplified block diagram of the power isolation and the isolation of the HDMI signals. Section 1 through Section 5 details the various signals in the HDMI protocol and how each signal is isolated using the ADN4624, ADuM1252, ADuM4070, ADuM321N, and ADuM1252/ADN4622 devices as shown in Table 1.

The design represents an isolated source application. In this scenario, long cables are expected to be driven and, therefore, the AD8195 HDMI 1.3a buffer from Analog Devices is used to enhance the cable driving capabilities of the isolator. In the Common Variations section, another version of the board is described, which does not make use of the buffer, more suitable for isolated sink or compact embedded applications where short printed circuit board (PCB) traces connections are driven by the ADN4624 Gbps isolator.

Step 1: Power

In the EVAL-CN0571-EBZ, an external supply must be connected to the Type C USB port to power all the ICs in the board. The minimum power that an HDMI source guarantees is limited by the HDMI standard to 275mW (5V at 0.055mA), not enough to power all the ICs in the EVAL-CN0571-EBZ. In a most common case scenario, and, therefore, in an isolated HDMI source application, where isolation is embedded in the board of the video transmitter (source), the power is not coming from an HDMI cable but from an on-board DC-DC or linear converter. Therefore, the power is not limited, and the accessory Type C USB connector can be removed by the design.

The Type C USB port provides the necessary 5V supply rail to power the board. The 3.3V and 1.8V voltage rails in the sourcefacing side of the barrier are generated by two ADP1707 linear dropout regulators. Sufficient power must also be provided to any circuitry located on the isolated side. To meet these requirements while maintaining galvanic isolation, the EVAL-CN0571-EBZ uses the ADuM4070, a 2.5W regulated DC-DC isolated power supply controller with an internal metal-oxide semiconductor field effect transistor (MOSFET) driver combined with an external push-pull transformer (see Figure 4).

The ADuM4070 based regulated push-pull converter in the EVALCN0571-EBZ utilizes two ferrite beads for filtering and suppression of electromagnetic interference (EMI) and common-mode noise.

Two RC snubbers are designed, tested, and optimized to minimize the oscillations resulting from the ringing of the transformer primary leakage inductance with the C_OSS of the MOSFET at turn-off, and the ringing of the transformer secondary leakage inductance with the rectifying diode reverse capacitance at turn-off, for an integration in an ideal low noise, low radiation environment.

The ADuM4070 can deliver the required current at up to a maximum ambient temperature of 105°C.

The isolated power coming from the regulated push-pull isolated converter configuration is provided to the HDMI sink on the DDC +5V line, the ADuM1252 I²C isolator used for DDC isolation, the ADuM321N digital isolator used for HPD and power enable isolation, and the two LTC3309A buck converters.

The first LTC3309A switching regulator is used to buck the 5V voltage down to 1.8V to power the ADN4624 V_DD2 supply. The other LTC3309A is instead used to convert 5V down to 3.3V to power the optional ADuM1252 I²C isolator used for CEC isolation and the AD8195 buffer.

The choice of using a high-efficiency switching regulator on the secondary side of the barrier to buck the voltages to 3.3V and 1.8V comes from the limited 2.5W isolated power availability and to keep all components at a reasonable cool temperature during normal operation.

The +5V signal on the DDC line must only be provided to the HDMI sink when an HDMI source is connected. The +5V signal from an HDMI source is transmitted across the isolation barrier using one of the iCoupler^® channels of the ADuM321N. This +5V signal is used in combination with a negative channel metal-oxide semiconductor (NMOS)-based inverter and a positive channel metal-oxide semiconductor (PMOS) to control the delivery of the +5V signal to the HDMI sink only when the above condition is met.

Step 2: Hot Plug Detect (HPD)

When an HDMI source device is connected to an HDMI sink device, the sink device receives a +5V signal, indicating that a source is connected. In response to this signal, the HDMI sink asserts the HPD signal, which is transmitted back to the source device. This indicates that the sink is correctly connected, and that it is ready to accept commands from the source through the DDC.

Figure 5 shows the HPD implementation on the EVAL-CN0571-EBZ reference design.

In the EVAL-CN0571-EBZ, the forward channel of the ADuM321N digital isolator is used to enable the 5V power to the output HDMI connector (facing the sink), only when an input HDMI cable is connected. In an isolated source application, the forward channel can instead be used as a power enable when the module or main processor goes into sleep mode.

The backward channel of the ADuM321N digital isolator is used to transmit the HPD signal across the isolation barrier from the sink to the source. A 4.7kΩ pull-down resistor on the input prevents the HPD signal from asserting when a sink device is not connected. A 1kΩ series resistor on the output is used to meet the 1kΩ ±20% output resistance specification for the HPD signal in the HDMI standard. This 1kΩ series resistor is not necessary in embedded applications. A 4.7kΩ pull-down resistor on the output prevents the HPD signal from asserting if a source is connected before the EVAL-CN0571-EBZ circuitry is powered correctly.

To enable the power flow to the sink, a discrete load switch is designed with an NMOS and a PMOS transistor. The NMOS serves as an inverter while the PMOS as the actual load switch. Analog Devices offers a variety of load switch ICs in its portfolio. An example is the MAX891, which can also act as a programmable current limiter, offering a rugged overcurrent protection.

Step 3: Display Data Channel (DDC)

The DDC is used for configuration and status exchange between the source and sink. The HDMI source device uses the DDC to read the extended display identification data (EDID) from the sink device. The EDID contents determine what audio/video formats are possible at the HDMI sink. The DDC channel is also used in the implementation of High-bandwidth Digital Content Protection (HDCP). The bidirectional DDC follows the requirements of a standard mode I²C bus, operating at a clock rate of 100kHz.

The DDC channel is isolated in the EVAL-CN0571-EBZ using the ADuM1252 bidirectional I²C isolator as shown in Figure 6. The serial clock (SCL) line requires a source pull-up of 47kΩ and a sink pull-up of 1.8kΩ. The serial data (SDA) line requires a sink pull-up of 1.8kΩ, with no source pull-up (since integrated in every HDMI compliant source).

Step 4: Transition Minimized Differential Signaling (TMDS)

The video and audio data in HDMI are transmitted from source to sink using four lanes of TMDS. The TMDS signals consist of three data pairs and one clock pair: TMDS_DATA0±, TMDS_DATA1±, TMDS_DATA2±, and TMDS_CLK±. The three differential data pairs transmit 10 bits per clock period and carry the high-speed video and audio data. The TMDS clock and data lines are implemented with the CML physical layer.

The coupling networks shown in Figure 7 allow reliable translation between CML and LVDS voltage levels. Following the coupling between the CML and the low-voltage differential signal (LVDS) physical layer, the ADN4624 2.5Gbps LVDS isolator is used to isolate the TMDS signals.

For CML to LVDS coupling, use 50Ω pull-up resistors to correctly terminate the CML pairs to the 3.3V supply. Series AC-coupling capacitors are required to remove the CML DC common-mode voltage (3.1V) that is not compatible with the absolute maximum voltage of the input data pin of the LVDS isolator. The EVAL-CN0571EBZ circuit note uses 10nF capacitor AC coupling capacitor for the purpose. A resistor divider per each line made of a 10kΩ pull-up resistor to 1.8V and a 13kΩ pull-down resistor to ground biases the common mode of the LVDS signals to 1V, which is the optimum point minimizing the resulting deterministic jitter. Two series 62Ω damping resistors are used, between the AC-coupling capacitors and the common-mode bias network, to reduce reflections caused by the capacitive input of the isolator. In the case of isolated source applications, the optimum coupling network must follow the design guidelines of the processor itself. Sometimes, video transmitters can be either configured both for DisplayPort and HDMI protocols and, therefore, their output is always AC-coupled, even though the standard TMDS are DC-coupled and do not require any AC coupling. In that case, the optimum CML to LVDS network would be a T-termination to 1V.

For LVDS to CML coupling, use a minimum of 10nF capacitors to remove the DC common-mode voltage of the ADN4624 LVDS outputs. A high capacitance value for the AC coupling capacitor has a better long-term DC wander effect and series impedance, but a worse equivalent series resistance (ESR) and, therefore, a resonance point at lower frequencies. A good compromise, for the LVDS to CML coupling network is a value in between 10nF to 100nF. The CML inputs at the HDMI sink are terminated with 50Ω on each line to the supply rail of the sink. This supply referenced termination removes the need of biasing resistors in the LVDS to CML coupling block.

The ADN4624 does not include any equalization or preemphasis capabilities to drive long cables and recover from resulting channel insertion losses. To enhance the capabilities of the isolator and recover the intersymbol interferences (ISI) jitter, an HDMI repeater or signal conditioner can be used. The EVAL-CN0571-EBZ makes use of the AD8195 HDMI buffer for this purpose. For maximum cable length driving capabilities, refer to the AD8195 data sheet.

Step 5: Consumer Electronics Control (CEC)

The CEC signal is optional. It is a protocol that allows the high control functions of all connected audiovisual products (for example, remote control of a television to set up a DVD player) to be accessed by any device in the user environment. The physical layer of the CEC protocol is a bidirectional multipoint 3.3V single-ended bus with up to a maximum of 10 devices. The minimum bit period on the CEC bus is 400µs. The HDMI specification specifies a pull-up of 27kΩ for the CEC line.

As shown in Figure 8, the SDA bidirectional channel of the 3.3V powered ADuM1252 isolator is used to provide isolation of the CEC signal. The SCL channel is not used and is tied by means of a 2kΩ pull-up resistor to the supply rail. Each side needs to be connected to a pull-up resistor of 27kΩ. The CEC standard specifies a maximum off state leakage current of 1.8µA. To ensure that, a series Schottky diode is used on the primary side to limit the off state leakage current while the EVAL-CN0571-EBZ is unpowered. The secondary side 27kΩ resistor is integrated in the AD8195 HDMI buffer, thereby the ADuM1252 is connected straight to it without requiring any external pull-up.

The CEC channel can be implemented using a multiple channel isolator such as the ADuM6422A. The implementation of this solution is shown in Figure 9. This can be useful when compact applications are desired and bill of materials (BOM) minimization is important. The digital isolator outputs are push-pull and not suitable for bidirectional multipoint communication. A series of Schottky diodes and pull-up resistors are used to convert these to open-drain outputs. The reverse bias Schottky diodes allow the CEC line to be pulled low by the ADuM6422A V_OB and V_OC outputs (as shown in Figure 6), while remaining high-impedance during a logic high. The low 0.12V forward voltage drop of the BAT60 Schottky diode minimizes the impact on the noise margin during a logic low.

On the HDMI source side, to prevent the circuit from latching, a bipolar junction transistor (BJT) Q1 is used. This is polarized by the resistor divider and the Schottky diode (R2, R3, D1) slightly above its maximum base emitter voltage (VBE) threshold. The conduction status of Q1 depends then on its emitter voltage. When the VOC output is driven low by the sink facing side, the V_OL is increased by an offset because of the forward voltage of the Schottky diode (D2) and the drop on the 3.9kΩ resistor. The resistor is sized as such to generate a low-voltage V_VOL2, during backward communication, which keeps Q2 off and prevents latching to happen. The value of the CEC logic low during backward communication can be computed as follows:

V_OL2(CEC) = V_F(I_bias) + I_biasR₅ + V_OL(I_bias) ≈ 0.6 V

where I_bias can be approximated as,

The BAS40 Schottky diodes are used for temperature compensation and to limit off state leakage current while the circuitry is unpowered.

Summarizing, we can distinguish two modes of operation as follows:

• During forward communication, it is the source side driving the CEC line, and the communication directionality is from the source to the sink. If the source CEC is asserted, a low-logic value turns the BJT on and Logic 0 is transmitted to the other side of the barrier, thanks to the digital isolator top channel. When the source CEC is released, the output cannot go immediately to high level because of the remaining low-level signal caused by the bottom channel transmitting backward Logic 0. Therefore, it raises to VBE of Q1, Q1 goes in high impedance and then it is released.
• During backward communication, it is the sink driving the CEC line, and the communication directionality is from the sink to the source. If the sink CEC is asserted, the offset generated by D2 and the series resistor R5 keeps Q1, biased just above its threshold, off and prevents the circuit from latching. If the sink CEC is released, D2 is reverse biased, and the CEC line can raise to 3.3V, thanks to its 27kΩ pull-up resistor.

The CEC circuit in the image forms a discrete I²C/bidirectional isolator with two unidirectional channels (one backward and one forward) of a digital isolator. The values of the resistors and the behavior of the circuit were simulated with LTspice and the circuit functionality is verified in laboratory at room temperature

Layout Guidelines

When dealing with high-speed isolation, the layout becomes part of the solution and has a significant impact on the performance of the circuit. The layout of the EVAL-CN0571-EBZ reference design is optimized for superior signal integrity. The following is a subset of the most important layout guidelines to consider when designing a circuit for the isolation of HDMI 1080p/60Hz.

• Differential traces that carry the TMDS signals must be designed with a controlled differential impedance of 100 ± 15% ohms.
• If microstrip traces are used, there must be a continuous reference plane on the PCB layer directly below the traces.
• If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stackup.
• Interlayer vias introduce impedance discontinuities that can cause reflections and the worsening of the jitter on the signal path. Therefore, it is preferable to route the TMDS lines exclusively on one layer of the board. If vias are unavoidable, place multiple via ground return paths very close to minimize the impedance discontinuity.
• To prevent unwanted signal coupling and interference, route the TMDS signals away from other signals and noise sources on the PCB.
• Both traces of the same differential pair must be equal in length to minimize intrapair skew. Excessive intrapair skew can introduce jitter through duty cycle distortion (DCD).
• Any group of four TMDS channels (input or output) must have closely matched trace lengths to minimize interpair skew. Severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on the FR4 material.
• The length of the TMDS traces must be minimized to reduce overall signal degradation. Commonly used PCB material, such as FR4, is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through ISI.
• Keep the CML to LVDS conversion network as close as possible to the isolator to minimize the length of the unwanted parasitic stub in-between. Use 0201 components and place the outer coupling networks 45 degrees angled to keep all the stubs at the same trace length.
• Use guard traces or ground planes between the TMDS pairs. This is to minimize crosstalk, electromagnetic radiation, and unwanted signal coupling or interference.