CN0320

Receiver Architecture

A direct conversion (also known as a homodyne or zero IF) architecture for a receiver is presented in this circuit note. Direct conversion radios perform just one frequency translation compared to a superheterodyne receiver that can perform several frequency translations. One frequency translation is advantageous because it:

• Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption
• Avoids image rejection issues and unwanted mixing products; one LPF at baseband is all that is needed
• Has high selectivity (adjacent-channel rejection ratio [ACRR])

Figure 1 shows the basic simplified schematic of the system that consists of an integrated quadrature demodulator with fractional-N PLL and VCO followed by programmable low-pass filters with variable baseband gain. The last part of the signal chain is an anti-aliasing filter and a dual A/D converter.

Ideally, the input of the first stage and the output of the last stage should set the dynamic range (signal-to-noise ratio) of the system. Practically, this may not be the case.

IQ Demodulator, Fractional-N PLL and VCO

The input signal is applied to the ADRF6801 quadrature demodulator, where the frequency is translated to a zero IF. The ADRF6801 has its own on-chip frequency synthesizer that provides the required LO. This frequency synthesizer consists of a fractional-N PLL and VCO, which while in the standard closed loop mode, has an LO frequency range from 750 MHz to 1150 MHz.

The ADRF6801 uses two double-balanced mixers, one for the I channel and one for the Q channel. The LO provided to the mixers is generated using a divide-by-two quadrature phase splitter. This provides the 0° and 90° signals for the I and Q channels , respectively. There is about 5 dB of conversion gain provided by the ADRF6801 from the RF input to the baseband I and Q outputs.

Low-Pass Filter, Baseband Variable Gain Amplifier (VGA), and ADC Driver

The low-pass filtering, baseband gain, and ADC driver functions are all achieved using the ADRF6510. The signal, now in its separate I and Q paths, is applied to the ADRF6510 where the signal is first amplified by the preamplifier, then low-pass filtered to suppress any unwanted out-of-band signals and/or noise, and finally amplified by the VGA.

Each channel of the ADRF6510 can be broken up into three stages:

• Preamplifier
• Programmable low-pass filter
• VGA and output driver

The preamplifier has a user-selectable gain, via the GNSW pin, of either 6 dB or 12 dB. The low-pass filter can be programmed for a corner frequency of 1 MHz to 30 MHz in 1 MHz steps via the SPI port. The VGA has a 50 dB gain range, with a 30 mV/dB gain slope. The gain of the VGA is controlled via the GAIN pin, and it can range from −5 dB to +45 dB when the GNSW pin is pulled low to +1 dB to +51 dB when the GNSW pin is pulled high. The output driver has the ability to drive 1.5 V p-p differential into a 1 kΩ load while maintaining an HD2 and an HD3 of better than 60 dBc.

The maximum continuous wave (CW) signal that can be applied to the low-pass filters, while still maintaining acceptable HD levels in the ADRF6510, is 2 V p-p . while the gain is minimum (GNSW = 0 V and GAIN = 0 V).

From the ADRF6510, the IQ signal can be applied to an analog-to-digital converter (ADC), such as the AD9248, but not before some passive low-pass filtering is applied between the stages.

Anti-Aliasing Filter

The I and Q signals go through an anti-aliasing filter that helps to:

• Reduce out-of-band noise
• Reduce output noise of the ADRF6510 (especially at higher gains)
• Reduce charge kickback from the ADC
• Reduce out-of-band blockers (although they should have been reduced by the filtering on the ADRF6510)

The anti-alias filter is a low-pass filter designed to have a corner ranging from about 30 MHz to 120 MHz. A lower corner frequency could be chosen if the spectral content of the signal is known to be something less than 30 MHz.

A total of five anti-aliasing filters were tested in the system. The first three anti-aliasing filters tested were differential RC types, shown in Figure 2. Filter 1 had R = 33 Ω and C = 18 pF. This created a low pass corner of approximately 134 MHz.

Filter 2 had a R = 33 Ω and C = 39 pF, which created a low pass corner of 62 MHz. Finally, Filter #3 had an R = 33 Ω and C = 68 pF, which created a corner of 35.5 MHz. Filter 4 in Figure 3 was an LC filter with a corner frequency of 33 MHz, and Filter 5 in Figure 4 was an RLC filter also with a corner frequency of 33 MHz.

A/D Converter

From the anti-aliasing filter the signal is applied to the ADC. The AD9248 dual 14-bit, 65 MSPS 3 V ADC features high performance sample-and-hold amplifiers and an integrated voltage reference.

Measurement Results: EVM of ADRF6510 and ADRF6510/ADRF6801Combination

A 4-QAM, 5 MSPS modulated signal was applied to the input of the ADRF6801quadrature demodulator and the error vector magnitude (EVM) was measured. Two AD8130-EBZ evaluation boards were used to convert the differential outputs of the ADRF6801 and the ADRF6510 to single-ended signals. For more information on the test setup, see the Circuit Evaluation and Test section.

EVM is a measure of the quality of the performance of a digital transmitter or receiver and is a measure of the deviation of the actual constellation points from their ideal locations, due to both magnitude and phase errors as shown in Figure 5.

Figure 6 shows the EVM vs. the input power to the ADRF6801 with only the ADRF6801, and the ADRF6801 followed by the ADRF6510. For the ADRF6801 and ADRF6510 curve, the gain changed on the ADRF6510 to maintain 1.5 V p-p output voltage as the input power to the ADRF6801 was swept. The preamplifier gain on the ADRF6510 is set to 6 dB.

When the ADRF6801 is tested alone, note that for high input signal levels the EVM does not degrade until about +5 dBm input power. But when the ADRF6801 is driving the ADRF6510, the EVM starts to degrade at about 0 dBm input power. This is because the low-pass filters on theADRF6510 can only handle 2 V p-p, which is 1 V p-p at the input pins of the ADRF6510 when the preamp gain is set to 6 dB, and the analog gain is at minimum. Signal levels beyond this begin to cause distortion which degrades the EVM.

For low input signal levels, the SNR becomes smaller and starts to degrade the EVM measurement. The EVM started to degrade at about −25 dBm when the ADRF6801 was tested alone. However, when the ADRF6801 is driving the ADRF6510, the EVM does not start to degrade until −40 dBm. There is degradation of EVM when measuring both parts at low signal levels, mostly due to the noise introduced by the ADRF6510. However, the floor of the bathtub is flatter and more consistent, and the ability to discern smaller signals is much better when the ADRF6801 is driving the ADRF6510, due to the baseband variable gain.

More comprehensive EVM measurements for the ADRF6510 and the ADRF6801 can be found in each respective data sheet.

Measurement Results: Complete Signal Chain Including ADC

For Figure 7 to Figure 16, the signal chain includes the ADRF6801, ADRF6510, and the AD9248. All three parts were dc coupled to each other. The common-mode voltage between the ADRF6801 and the ADRF6510 was 2.6 V. The common-mode voltage between the ADRF6510 and the AD9248 was 2.0 V. Full-scale for the ADC was 2 V. The input power to the ADRF6801 was swept, and the gain of the ADRF6510 was varied to set the proper signal level at the ADC input, −3 dBFS. SNR, SFDR, THD, HD2 and HD3 were measured using the ADC and the Visual Analog software. The sampling rate was set to 65 MSPS from an Agilent 8665B low phase noise signal generator. Two different filter bandwidths of the ADRF6510 were used: 5 MHz and 30 MHz. Also, the preamp gain of the ADRF6510 was changed from 6 dB to 12 dB. The RF provided to the ADRF6801 was 895 MHz, and the LO was set to 900 MHz, thereby creating a 5 MHz IF tone. A 100 MHz reference was used. The reference was divided by 4 to make a PFD frequency of 25 MHz. The 100 MHz signal was generated by the Model 119-3651-00 Wenzel crystal oscillator.

The data collected in this circuit note shows that the SNR (71.6 dB) and SFDR (80.5 dBc) performance of the AD9248 ADC exceeds that of the ADRF6801 and ADRF6510 combination. The overall SNR and SFDR of the system is limited primarily by the output noise of the ADRF6510, which is specified as −130 dBV/√Hz at 20 dB of gain with a filter bandwidth of 30 MHz, measured at mid-band. (For more information of the noise vs. gain and bandwidth settings of the ADRF6510, please refer to the ADRF6510 datasheet).

ADRF6510 filters exhibit compression at high input power levels (in this case at low gains), which increases harmonic distortion. At low input power levels the ADC is essentially measuring the output noise floor of the ADRF6510, and the HD2 and HD3 tones are below the noise floor. The output noise floor of the ADRF6510 is raised due to the higher gain at lower input powers.

Figure 7 and Figure 8 show the SNR of the entire signal chain including the ADC. At low power levels, the SNR degrades almost dB-for-dB. The gain of the ADRF6510 is at its maximum and can no longer supply −3 dBFS at lower input power levels. The signal decreases in amplitude, while the noise remains relatively constant; hence the decrease in SNR. The SNR approaches a constant level when there is enough signal and enough gain to achieve −3 dBFS. Best SNR was achieved with anti-aliasing Filter 3, although only about 1 dB was spread between all filters, except for anti-aliasing Filter 1, that caused poorer SNR than the rest of the filters.

SNR degrades sharply at the highest of input power with the ADRF6510 filters set to 30 MHz, as shown in Figure 8. This is due to compression in the ADRF6510 filters that causes HD2 and HD3 to degrade suddenly, and the entire noise floor rises drastically.

Figures 9 and 10 show SFDR of the entire system for the various anti-aliasing filters. Filter 4 and Filter 5 perform very poorly, with an SFDR of 40 dB across most of the input power range. This is due to the HD3 tone limiting the SFDR. For the other anti-aliasing filters, SFDR was more than 60 dB for most of the range. There is a slight degradation at the lower input powers due to the main tone not being at −3 dBFS.

At the high input power levels, the SFDR is limited by the harmonics caused by compression in the ADRF6510 filters.

Figure 11, Figure 12, Figure 13, and Figure 14 show the HD2 and HD3 of the system. Anti-aliasing filters 4 and 5 performed poorly again, achieving an HD2 performance of about −55 dBc and only −40 dBc for HD3. Filters 1, 2, and 3 performed much better, yielding results of better than −70 dBc for HD2 and HD3.

At the low end of the input power range, the HD2 and HD3 components were so small that they were less than the noise floor, and what was actually recorded was the noise. After the gain of the ADRF6510 was lowered enough to decrease the output noise which in turn revealed the HD tones, proper measurements could be made.

At the high end of the input power range, HD2 and HD3 degraded significantly. This is due to compression in the ADRF6510 filters.

Anti-Aliasing Filter Performance Summary

Five anti-aliasing filters were tested and shown. The RC type of filter had much better harmonic distortion performance compared to the LC and RLC types. When using the ADRF6510 to drive the AD9248, it is recommended to use an RC filter type with a corner frequency as low as possible to achieve the best performance in the application across all the metrics.

Common-Mode Sweeps

It is possible to operate the common-mode voltage between the output of the ADRF6510 and the input of the AD9248 at something other than 2 V and still maintain good performance.

Figure 15 and Figure 16 show all the standard metrics over a common-mode sweep. The system maintains good performance for common-modes between 1.5 V and 3 V. The degradation for low common-mode voltage is primarily due to the ADRF6510, while the degradation at high common-mode voltage is caused by a combination of the ADRF6510 and the AD9248. Setting the common-mode voltage at 2.25 V for the ADRF6510/AD9248 is optimum.