CN0564

I²C Signaling Standard Summary

I²C is a serial protocol for a bidirectional two-wire interface to connect low speed devices like electrically erasable programmable read-only memory (EEPROM), analog-to-digital and digital-to-analog converters, input/output (I/O) interfaces, and other peripheral to an embedded processor. It is a very popular go-to for sensors because of its simplicity and expandability; multiple devices can exist on the bus, each with its own unique address. It requires just two wires to transfer data between devices. The two wires include:

• SCL - the serial clock signal line
• SDA - the serial data line for sending and receiving data between the controller and peripheral
  
  

The SCL and SDA signals are open drain logic, with logic levels and timing specifications defined in the I²C bus specification and user manual.

The number of peripheral devices, which can exist on a given I²C bus is limited by the address space and by the maximum total bus capacitance of 400 pF. The relatively high impedance and low noise immunity of open drain logic requires that all peripherals have a low impedance connection to a common ground return, and maximum bus length is restricted to approximately one meter at 100 kHz.

The CN0564 features differential transceivers that extend the length of the bus up to 1200 meters, and tolerate up to ±15 V common-mode difference between the controller and peripheral. The capacitances of the controller side and far side bus segments are isolated from each other and from the differential link, minimizing the impact on bus rise and fall times.

SDA is inherently bidirectional, with direction of data flow between controller and peripheral changing direction over the course of a transaction. I²C supports clock stretching where a peripheral device may hold SLCK low to slow down the clock rate. Thus, SCL is also bidirectional. The bidirectional nature of I²C makes it inconvenient to extend with buffers, isolate, or translate to other physical layers, requiring multiple logic levels and other nonstandard techniques. Analog Devices, Inc. also offers a suite of solutions that deal with bus buffer complexities.

Common I²C bus speeds are 100 kHz for standard mode (Sm) and 400 kHz for fast mode (Fm). The LTC4331 controller interface supports all common I2C clock rates up to 1000 kHz.

At low data rates and with short cables, latency is effectively transparent. At high clock frequencies and/or longer cable lengths, propagation delays begin to erode timing margin. The CN0564 is compatible with controllers that support clock stretching, which effectively slows down the clock frequency such that timing requirements are met, regardless of cable length. 

SPI Signaling Standard Summary

The SPI is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. Unlike I²C, SPI is not rigorously defined; a wide variety of clock frequencies, logic levels, and timing relationships are supported, requiring careful inspection of the controller and peripheral specifications. SPI is full-duplex communication, wherein data can flow from the controller to peripheral and vice versa, simultaneously.

The SPI physical layer typically consists of four signals:

• SCLK - serial clock, usually driven by the controller
• MISO - controller data input, peripheral data output
• MOSI - controller data output, peripheral data input
• CS - chip select enables communication with a peripheral. One CS line is required per peripheral device.
  
  

SPI pins use push-pull logic (rather than open drain), and the logic level between a controller and peripheral must match. Each peripheral device requires its own CS signal, further complicating physical extension of the SPI bus.

Four different timing relationships between clock and data are supported, referred to as modes 0, 1, 2, and 3 that correspond to the four possible clocking configurations. Each transaction begins when the chip select line is driven to logic low (chip select is typically an active-low signal). The exact relationship between the chip select, data, and clock lines depends on how the clock polarity (CPOL) and clock phase (CPHA) are configured. The four modes are summarized in Figure 2.

The LTC4332 supports up to three remote peripherals, each with their own CS line. Each peripheral’s SPI modes can be independently programmed to mode 0, 1, 2, or 3. The LTC4332 makes the extension of the SPI bus simple and requires only two twisted pairs to support the several signals. Data is transparently transmitted from the controller to the peripheral, however a one word delay is introduced in the data from peripheral to controller. Refer to the One Word Latency – SPI Read Command section for more details.

System Topology

The CN0564 uses the LTC4331 and LTC4332 to extend I²C and SPI signals up to 1200m. Each link consists of a pair of devices, with the controller side configured in local mode (REMOTE pin tied low) and peripheral side device configured in remote mode (REMOTE pin tied high).

The LTC4332/LTC4331 encode the SPI/I²C signals from the controller into differential signals which are then transmitted through the twisted pair of cables. At the remote end of the cable, the differential signals are received by the remote LTC4332/LTC4331 and decoded back to SPI/I²C, which is then routed to the remote peripheral device. In normal operation, the remote peripheral device mirrors the events produced by the local controller.

Selectable Baud Rates

The LTC4332/LTC4331 can change its link baud rate which is the speed at which data propagates between the local and the remote link using a selectable Speed Index (shown in Table 1 & Table 2). This speed index is set by configuring the link and interface timing select pins, SPEED1 and SPEED2, which are both 3-State inputs.

Selectable baud rates over the cable allow balancing performance versus cable length depending on the application requirements. However, both sides of the link must be set to the same speed configuration.

Increased Cable Length Transmission

The LTC4332/LTC4331 utilize high speed differential transceivers to communicate over a link of up to 1200m in length. I²C/SPI signals are converted to differential signals for high speed, high quality signal transmission, noise immunity, as well as common mode rejection. For a given SPEED setting, cable length specifications given in Table 1 for LTC4331 and Table 2 for LTC4332 must be adhered to or the link will not operate. The values in the table were recorded using a Cat5E Ethernet cable in a lab environment. Note that the actual maximum cable length depends on type of cable and application environment.

Common Mode Voltage and ESD Robustness

The differential transceiver operates over an extended common mode range of ± 25V for SPI extenders and ± 15V for I²C extenders making it suitable for noisy environments or systems with ground potential differences (refer to Figure 1).

The interface pins (LTC4331 A & B pins, LTC4332 A,B,Y & Z pins) are fault protected to ±60V. The interface pins also feature exceptionally robust electrostatic discharge (ESD) protection to ±40kV HBM ESD (Human Body Model test) with respect to GND and VCC (with a 4.7μF capacitor to GND) without latch-up or damage, during all modes of operation, or while unpowered.

Both LTC4331/LTC4332 ESD also survive the International Electrotechnical Commission (IEC) ESD and EFT (Electrical Fast Transient) tests. The IEC ESD stress exceeds that of the HBM test in peak current, amplitude, and rise time, while the EFT test provides a prolonged repetitive stress. This level of protection ensures that the LTC4332/LTC4331 are robust under a wide range of real-world hazards.

One Word Latency — SPI Read Command

Propagation delay is also a concern for SPI communications, and limits the maximum bus speed when simultaneously reading and writing. The SPI extender solution deals with this issue by inserting one word of latency during read accesses only. Because the data sent from the SPI controller to the peripheral experiences the same delay as the controller-initiated interface clock (SLCK), both remain in sync across the entire data link.

In the opposite direction, the peripheral device sends MISO data to the controller only when the first clock edge reaches the peripheral device. This data experiences a second delay on its way back to the controller, so the MISO data is out of sync by twice the cable’s propagation delay. Physically distant devices need a dramatically reduced clock rate to accommodate the propagation delay within each bit width. To overcome this limitation, the LTC4332 introduces a shift register into the MISO signal path, as shown in Figure 3.

As a result, SPI write requests to remote peripheral devices are software transparent, but SPI read requests to remote peripherals incur a one word latency, meaning the read command needs to be extended by one word. If not, the last word is lost in the LTC4332 MISO shift register when the chip select is de-asserted. The WORD_LENGTH register (see the register map in the data sheet for LTC4332) indicative of the depth of the shift register in MISO signal path on LTC4332, dictates when the SPI controller begins receiving valid data on the MISO line. For example, if the WORD_LENGTH is 8, the user would begin receiving valid MISO data 8 clock cycles after CS is asserted.

Fault Monitoring

The LTC4331/ LTC4332 LINK pin indicates the state of the communication link, and is driven low to indicate that the remote I²C/SPI bus has joined the local I²C/SPI bus.

The LTC4331/ LTC4332 support interrupt signals, ALERT on pin on the LTC4331 and INT on the LTC4332. These signals are mirrored from the remote bus to the local bus. On the remote end, the interrupt pins are inputs that can be connected to the interrupt output of the connected I²C/SPI peripheral. On the local side, ALERT/INT operate as an open-drain output that can be connected to a shared local interrupt line. If enabled, the local LTC4331/LTC4332’s control interface uses the ALERT/INT pin to report link and fault events. The local side ALERT/INT output is the logical AND of the remote ALERT/INT and the internal endpoint interrupt signal.

The local side LTC4331/LTC4332 can also trigger a remote side reset by holding the ON pin low for a minimum of 180ms. If the link is disconnected, the remote LTC4331/LTC4332 is automatically reset after 180ms. A remote reset disables all remote side outputs until link communication is re-established.

LTC4331/LTC4332 Control Interface

To configure the control interface on the local side of the LTC4331/ LTC4332 link, a separate internal addressable peripheral is available. The internal interface on the local LTC4331 is assigned a unique I²C address by configuring the pins A1 and A2. The LTC4332 on the other hand, provides a separate chip select pin, SSC, that allows a user to communicate with the internal SPI addressable registers.

The LTC4331/LTC4332 control interface allows the speed configuration, link status, and interrupt / alert status to be read, as well as additional I²C/SPI specific options to be accessed. The LTC4331 can be configured to translate the I²C address to the remote peripheral, expanding the I²C address space and preventing address conflicts. The LTC4332 allows independent SPI mode configuration for each CS pin, as well as the word length (which determines the received data latency). Refer to the LTC4331 and LTC4332 datasheet for more information.

PCB Size

Increased component density in PCB designs leads to complex problems. To encode SPI or I²C, an additional microcontroller is normally required which increases both the solution cost and size, but by using the CN0564 there is no requirement for an additional microcontroller on the remote side. This allows for a smaller sensor solution that uses up less area on the PCB, reducing the overall cost of manufacturing and leaving more room for other components for additional features.

Expanding Sensor Interface Capabilities

Sensor interfaces for longer distance transmission have traditionally used analog signaling techniques, such as 0-10V or 4-20 mA. For example, in condition monitoring applications the integrated electronic piezoelectric (IEPE) sensor interface is the most common signaling standard used for vibration sensors. It supplies a constant current source to the vibration sensor, with the sensor output voltage read back on the same wire. This 2-wire system allows for simpler system design when transmitting AC signal content but provides no additional fault monitoring or configurability. The LTC4332/LTC4331, on the other hand, allow for flexible configuration, processing, and easy debugging during fault events directly on digital output sensors