Voltage Reference Scaling Technique Increases ADC Accuracy to Keep Costs Down

by Franco Contadini Download PDF

Abstract

In this design note a circuit uses a 10-bit ADC, voltage divider, and external reference to improve the ADC's virtual accuracy to 13 bits. The article shows a voltage scaling technique that extends 10-bit ADC range to 13 bits. The MAX159 10-bit ADC, MAX5420 voltage divider, and MAX6141 voltage reference are featured.

A data acquisition board, in order to provide flexibility, must be able to accommodate various input voltage ranges. Handling low amplitude signals generally requires an increase in the number of bits of resolution, increasing cost.

This application note describes a simple circuit that uses a low cost 10-bit ADC but increases the virtual accuracy to 13-bit.

Figure 1.

Figure 1.

1 LSB (least significant bit) for an ADC is FSR/2n, where n is the number of bit. FSR (full-scale range) depends from the amplitude of the voltage reference. The input voltage range of the external reference for MAX159, a low power, 108ksps serial ADC available in µMAX®-8 package, is 0 to VDD + 50mV. This large input range permits to accommodate different input range using a scaling technique.

The output of a low-cost 3-pin voltage reference is scaled using a digitally programmable voltage divider (MAX5420). This device provides four precision divider ratios of 1, 2, 4, 8. The ratio accuracy span from 0.025% to 0.5% according to the grade (A, B, C). The ratio is selected using the digital inputs D1, D0 as follows:

Table 1.
DIGITAL INPUTS
D1 D0 DIVIDER RATIO
0 0 1
0 1 2
1 0 4
1 1 8

The reference voltage MAX6141 provides an output voltage of 4.096V. The size of 1 LSB using a divider ratio of 1 will be 4.096/1024 = 4mV. This size change according the following table:

Table 2.
VREF(V) DIVIDER RATIO LSB(mV) VIRTUAL ACCURACY TO 4.096V FS
4.096 1 4 10-bit
2.048 2 2 11-bit
1.024 4 1 12-bit
0.512 8 0.5 13-bit

The effective resolution remains at 10 bits. But compared to a 4.096V FSR system, the virtual accuracy is improved. The size of 1 LSB remains greater than the typical converter noise floor (300µV), also with divider ratio of 8. This ensures that the ADC performances are not limited by the LSB's reduced size.



Author

Franco Contadini

Franco Contadini

Franco Contadini has over 35 years’ experience in the electronic industry. After 10 years as a board and ASIC designer, he became a field applications engineer supporting industrial, telecom, and medical customers and focusing on power and battery management, signal chains, cryptographic systems, and microcontrollers. Franco has authored several application notes and articles on signal chains and power. He studied electronics at ITIS of Genova.