AN-1340: ADF7023-J IEEE 802.15.4g/UBUSAir/FAN Firmware Module

Introduction

This application note describes the IEEE 802.15.4g (15d4g) firmware download module for the ADF7023-J transceiver IC. The firmware module adds the following features to the ADF7023-J:

• IEEE 802.15.4g physical layer (PHY) header formatting
• IEEE 802.15.4g compliant data whitening
• Transmitter (Tx)/receiver (Rx) rolling data buffer
• 4-byte to 1000-byte preamble
• ARIB STD T108 compliant clear channel assessment (CCA)

Figure 1 shows a block diagram of the ADF7023-J low power, 902 MHz to 958 MHz transceiver IC. The transceiver contains a custom microcontroller (MCU) core with a mask ROM, which implements packet handling functions and translates radio commands into internal control sequences. An additional 2 kB of program RAM (PRAM) is available and serves as program code memory. It enables the addition of radio controller commands to provide modified or extended functionality. The IEEE 802.15.4g firmware download module described in this application note is based on program code downloaded into this PRAM.

The PRAM block is volatile memory and must be reloaded each time the transceiver wakes up from sleep state. The PRAM locations can be accessed sequentially through the serial peripheral interface (SPI). The details of the code download mechanism are explained in the Code Download Sequence section.

The firmware download binary is rom_ram_7023_2_2_15d4g_R0p0.dat and is available from Analog Devices, Inc., at ftp://ftp.analog.com/pub/RFL/FirmwareModules/ADF7023.

The revision (R0p0) may change as new features are added.

The IEEE 802.15.4g firmware download module remaps several of the ADF7023-J registers and commands and extends the data sheet state diagram. See the Register Remapping section for more information.

Note that throughout this application note, multifunction pins (such as the ADCIN_ATB3 pin) are referred to either by the entire pin name or by a single function of the pin (for example, ATB3) when only that function is relevant.

Register Remapping

The firmware extends the ADF7023-J data sheet state diagram to include the 15d4g state, as outlined in Figure 2, and extends the firmware states, as defined in Table 3.

When the firmware module is downloaded and the 15d4g state is entered, some of the battery backup random access memory (BBRAM) registers take on new meaning, and some are rendered redundant. The remapped BBRAM registers are defined in Table 1. The command list is expanded, as defined in Table 2. The INTERRUPT_MASK_0 register and the INTERRUPT_SOURCE_0 register are also remapped while in the 15d4g state, as defined in Table 31 and Table 32.

Register Map Extension

The following sections detail the registers for use with the 15d4g firmware download.

CCA Control

ATB Control

IEEE 802.15.4G Packet Structure Control

Rolling Buffer Control

Test Mode Control

Other Registers

Register Descriptions

The values in Address 0x132 (the BB_PHR_LOW register) are read only. In receive mode, the values are copied in by the 15d4g firmware download module from a received packet. In transmit mode, the required PHR value for a transmit must be written to the TX_BASE_ADR register, and the firmware reflects those values back in Address 0x132.

The values in Address 0x133 (the BB_PHR_HIGH register) are read only. In receive mode, the values are copied in by the 15d4g firmware download module from a received packet. In transmit mode, the required PHR value for a transmit must be written to the TX_BASE_ADR register, and the firmware reflects those values back in Address 0x133.

Interrupt Mask and Source Configurations

Fast Tx/Rx Transitions

The download module supports fast transitions from PHY_ON_15d4 to PHY_TX_15d4 and PHY_RX_CCA_15d4. The fast transitions are achieved by the following sequence:

1. Issue CMD_SYNTH_CAL (0xEE) while in PHY_ON_15d4. A synthesizer calibration is performed at the programmed channel frequency, and the results are stored in BB_VCO_BAND_READBACK (Address 0x13B) and BB_VCO_AMPL_READBACK (Address 0x13C).
2. Enable synthesizer calibration overwrite by setting VCO_OVRW_EN (Address 0x3CD) = 0x3.

The CMD_PHY_RX_CCA_15d4 and CMD_PHY_TX_15d4 commands complete in a shorter time after this sequence, because a synthesizer calibration is no longer performed.

Note that it is good practice to periodically perform a full synthesizer calibration, which maintains optimum RF performance across fluctuations in operating temperature or battery voltage.

Clear Channel Assessment

For clear channel assessment, the CCA threshold is programmed into the BB_CCA_THRESHOLD register (Address 0x12B). If the measured RSSI is above this threshold, the channel is busy; if the measured RSSI is below this threshold, the channel is clear.

Evaluation of RSSI is automatically activated on entering PHY_RX_CCA_15d4. Multiple times per byte, the RSSI value is evaluated, and the CCA_LIVE_STATUS flag is updated to busy or clear. Therefore, after entering the PHY_RX_CCA_15d4 state, the RSSI value and a live CCA status are always updated, unless updates are turned off with CCA_BYPASS_UPDATE (Bit 0 of Address 0x129).

Note that there is a time lag until the first RSSI value is updated on first entering PHY_RX_CCA_15d4 state. Until the first RSSI value is updated, the previously measured RSSI value is retained. If this is undesirable, the BB_RX_RSSI register may be zeroed before entering PHY_RX_CCA_15d4.

On issuing CMD_CCA_START, the RSSI is evaluated and compared with the CCA threshold to determine if the channel is busy or clear, and the CCA_STATUS flag is updated accordingly.

CCA Timers

The CCA evaluation period is programmable in CCA_TIMER in the BB_CCA_CONTROL register. This is a timer in microseconds, as defined in Table 33.

The timer is initiated and the evaluation period is started by the CMD_CCA_START command. When the timer times out, or when the timer is interrupted by an incoming packet, the CCA interrupt is generated (if it is enabled). Note that there is an internal overhead on the timer modes that means the CCA evaluation period is somewhat less than the CCA timer evaluation value. Therefore, it is recommended that the user performs their own characterization tests to ensure that the actual CCA evaluation period matches their requirement, and if not, to select the next available timer, or extend the CCA evaluation time as discussed later in this section.

The CCA_STATUS is automatically cleared at the beginning of every evaluation period (channel free). If the CCA_LIVE_STATUS bit goes high (that is, RX_RSSI_READBACK exceeds CCA_THRESHOLD) at any stage during the evaluation period, the CCA_STATUS flag is automatically updated to busy.

CCA timer mode is generally used with automatic Tx (the BB_CCA_CFG_0 register, Bit 4 = 0).

If the channel is clear, and automatic Tx is enabled, the device transitions automatically to the PHY_TX_15d4 state (see Figure 3).

If the channel is clear and automatic Tx is not enabled, the CCA interrupt is generated, and the device remains in the PHY_RX_CCA_15d4 state, with CCA_STATUS set to free.

If the channel is busy, and the timer times out, a CCA interrupt is generated, and the device remains in the PHY_RX_CCA_15d4 state, with CCA_STATUS set to busy (see Figure 4).

It is important to note that the RSSI value is continuously updated and evaluated during each byte period once in the PHY_RX_CCA_15d4 state, unless updates are turned off with CCA_BYPASS_UPDATE (Bit 0 of Address 0x129). Therefore, if the channel had evaluated as clear, but automatic Tx was not enabled, the CCA continues to be assessed, and if the channel becomes busy, this is detected and CCA_STATUS is set to busy. This can be used as a default timer extension.

During CCA timer mode, incoming packets can be received. In the event of an SFD being detected, any running CCA timer is terminated, and the CCA interrupt is asserted after SFD detection. CCA_STATUS is set to busy. The packet continues to be received normally (see Figure 5).

If the CCA timer times out during the preamble or SFD of an incoming packet before the device has an opportunity to detect the SFD, that packet is lost, and the CCA interrupt is generated (see Figure 6).

Issuing Commands During Packet Reception

Take care when issuing CMD_CCA_START as there are certain conditions under which issuing the command, coincident with the start of preamble on an incoming packet, cause that packet to be lost. Minimizing this risk is discussed in the Potential Packet Loss when Issuing Commands section.

Dynamic IF Filter Bandwidth Setting During CCA Timer Mode

The functionality of the intermediate frequency (IF) filter bandwidth for Rx during CCA timer mode is discussed in this section.

Upon entering the PHY_RX_CCA_15d4 state, the receiver baseband filter bandwidth is selected from the BBRAM (Bits[7:6] of Address 0x115).

In CCA timer mode, the receiver baseband filter can be automatically changed for CCA RSSI by setting ENABLE_IFBW_AUTO_SWITCH (Bit 5 of CCA_CFG_1, Address 0x12A) to 1. Then, the filter bandwidth automatically switches to the CCA_FILTER_BW setting (Bits[6:5] of Address 0x129) when the CMD_CCA_START command (Address 0xB7) is issued.

Note that the IF of the receiver can toggle between 200 kHz and 300 kHz depending on the selected filter bandwidth.

The IF filter bandwidth of the receiver is switched back to its original BBRAM setting (Bits[7:6] of Address 0x115) when one of the following events occurs:

• If the CCA timer times out
• On issuing CMD_CCA_STOP
• On issuing CMD_PHY_RX_CCA_15d4
• On an incoming packet preamble detection if ENABLE_IFBW_SWITCH_ON_PREAMBLE = 1 (available only if the CCA and normal Rx IFBW are both on the 200 kHz IF frequency; requires 12-byte preamble).

On an incoming packet preamble detection, if ENABLE_IFBW_SWITCH_ON_PREAMBLE = 1, the receiver baseband filter switches back to its original Rx IFBW value for packet reception (see Figure 7). This is only available between filters on the 200 kHz IF (that is, 200 kHz, 150 kHz, and 100 kHz). There is also a minimum preamble requirement of 12 bytes to achieve this dynamic IFBW switching.

On an incoming packet preamble detection, if ENABLE_IFBW_SWITCH_ON_PREAMBLE = 0, the receiver baseband filter bandwidth is retained at its current value for the duration of the packet reception, and switches back at the end of packet reception.

If a 300 kHz IFBW is required for CCA, but the normal receive IFBW is 150 kHz, for example, the dynamic IFBW switching on preamble detect is not possible, because the CCA and RX filters are on different IF frequencies. In this case, ENABLE_IFBW_SWITCH_ON_PREAMBLE must be set to 0, and any packet arriving during the CCA time is received on the 300 kHz IFBW. The 150 kHz Rx IFBW is restored for subsequent receives.

False Preamble Detects During CCA Timer Mode

If a false preamble is detected while in CCA timer mode and ENABLE_IFBW_SWITCH_ON_PREAMBLE = 1, the receiver switches back to its original IFBW value for packet reception, as specified in IFBW (Bits[7:6] of Address 0x115).

If SFD is subsequently not detected, this is a false preamble detect, and the firmware takes the following action:

• If ENABLE_IFBW_AUTO_SWITCH = 1, once SFD is not detected, the ADF7023-J sets the IF filter bandwidth to the CCA_FILTER_BW setting (Bits[6:5] of Address 0x129).
• If ENABLE_IFBW_AUTO_SWITCH = 0, once SFD is not detected, the ADF7023-J sets the IF filter bandwidth to the original IFBW value for packet reception, as specified in IFBW (Bits[7:6] of Address 0x115).

If a false preamble is detected while in CCA timer mode and ENABLE_IFBW_SWITCH_ON_PREAMBLE = 0, the receiver does not switch back during preamble.

If SFD is subsequently not detected, then this is a false preamble detect, and the firmware takes the following action:

• If ENABLE_IFBW_AUTO_SWITCH = 1, once SFD is not detected, the ADF7023-J sets the IF filter bandwidth to the CCA_FILTER_BW setting (Bits[6:5] of Address 0x129).
• If ENABLE_IFBW_AUTO_SWITCH = 0, once SFD is not detected, the ADF7023-J sets the IF filter bandwidth to the original IFBW value for packet reception, as specified in IFBW (Bits[7:6] of Address 0x115).

Command Access During PHY_RX_CCA_15d4 STATE

The ADF7023-J is controlled through commands, and command access is described in the ADF7023-J data sheet. The data sheet also describes the use of the status word to ensure that the communications processor is ready to accept a new command.

Potential Packet Loss when Issuing Commands

Take care when issuing commands in the PHY_RX_CCA_15d4 state while waiting for an incoming packet because of the asynchronous timing of the incoming packets.

There are certain conditions under which issuing a command, coincident with the start of preamble on an incoming packet, causes that packet to be lost. Commands involved are the following:

• CMD_PHY_RX_CCA_15d4
• CMD_PHY_TX_15d4
• CMD_PHY_ON_15d4
• CMD_CCA_START

To minimize the risk of losing an incoming packet, a PHY_RX_STATUS (Address 0x01F) byte is offered. Bit 0 of this byte highlights when preamble has been detected; Bit 1 indicates when SFD has been detected; and Bit 2 indicates when CRC is correct.

Upon entering the PHY_RX_CCA_15d4 state, these bits are set to 0. On preamble detection, Bit 0 is set to 1; on SFD detection, Bit 1 is set to 1; on CRC correct, Bit 2 is set to 1.

If a false preamble is detected (that is, a qualified preamble without a subsequent SFD), these bits are set to 0 and the search for preamble continues.

Any command that restarts receive resets these bits to 0.

Packet loss can be minimized by monitoring the PHY_RX_STATUS register and issuing commands only when PHY_RX_STATUS = 0.

However, while monitoring the PHY_RX_STATUS register method, there is still a condition under which packet loss is possible, where a preamble may have started in the air but is not yet detected by the device.

The two extremes of this condition are outlined in Figure 10 and Figure 11. The worst-case scenario occurs at the latest possible preamble qualification time, which is less than 4 bytes into the 4-byte preamble (see Figure 10). In this scenario, if a command (for example, CMD_CCA_START) occurs during the first 4 bytes of preamble in the air, the preamble acquisition is disrupted and packet loss may occur. The best-case scenario occurs at the earliest possible preamble qualification time, which is 1 byte into the preamble (see Figure 11). In this case, if the CMD_CCA_START occurs during the first byte of preamble, packet loss may occur.

Automatic ATB Control

The ATB1, ATB2, ATB3, and ATB4 pins on the ADF7023-J can be used to control external RF antenna switches. In some configurations, the switch control may or may not be the same for Tx and Rx. The firmware download gives complete control of the ATB pins during Tx and Rx to cover for such situations. This section provides configuration details of these four pins in receive and transmit modes.

Receive Mode

In the PHY_RX_CCA_15d4 state, the mapping of the control bits to configure the ATB pins is automatically controlled by Bits[7:5] in BB_ATB_CONTROL (Address 0x12D). Bits[7:6] control the ATB logic, and Bit 5 selects the driver, as shown in Table 34.

These control bits appear at the ATB1 and ATB2 pins as VDD control bits, or at ATB3 and ATB4 as 1.8 V control bits. The selection between V_DD or 1.8 V controls is made using RX_ATB_LEVEL (Bit 5 of BB_ATB_CONTROL).

Transmit Mode

In the PHY_TX_15d4, the mapping of the control bits to configure the ATB pins is automatically controlled by Bits[3:1] in BB_ATB_CONTROL (Address 0x12D). Bits[3:2] control the ATB logic, and Bit 1 selects the driver, as shown in Table 35.

These control bits appear at the ATB1 and ATB2 pins as V_DD control bits, or at ATB3 and ATB4 as 1.8 V control bits. The selection between V_DD or 1.8 V controls is made using TX_ATB_LEVEL (Bit 1 of BB_ATB_CONTROL).

Do not enable external PA/LNA in MODE_CONTROL (Register 0x11A) because this conflicts with the ATB control in 15d4g mode. If an external PA/LNA is to be used in 15d4g mode, control using the logic in BB_ATB_CONTROL.

Packet Structure in 15D4G Mode

The ADF7023-J firmware download module supports the MR_FSK PPDU header format without mode switching.

The packet structure is displayed in Figure 12.

In transmit mode, the ADF7023-J firmware module adds the requested number of preamble bytes, and inserts the requested SFD and PHR. If whitening is enabled, the PSDU is whitened. If 16-bit FCS is enabled, the 16-bit CRC is automatically calculated and appended to the transmit payload.

In receive mode, the preamble optionally generates a preamble detect interrupt and is not stored to packet RAM. The SFD is used for byte level synchronization, optionally generates an interrupt synchronous with PHR reception, and is not stored to packet RAM. PHR is received next, and depending on its contents, dictates the receive packet length, whether dewhitening is to be applied or not, and whether FCS is 16 bits or 32 bits. The 16-bit FCS case is handled automatically.

Preamble

The preamble is a 1010 sequence added to the start of the packet during transmission, and removed after receiving the packet. The preamble length is defined in bytes, with a programmable range of 4 bytes to 1000 bytes. It is configured by writing to the BB_NB_PREAMBLE_BYTES_HIGH register (Address 0x12F) and the BB_NB_PREAMBLE_BYTES_LOW register (Address 0x12E).

SFD

The SFD is a 2-byte word that is controlled by writing to BB_SFD_HIGH (Address 0x131) and BB_SFD_LOW (Address 0x130). The SFD takes on one of four valid options selected from Table 36. Note that the SFD is transmitted starting from Bit 0.

PHR

The PHR is a 2-byte word as defined in the PHR section in Figure 12. This word is controlled by writing the low byte to TX_BASE_ADR , and the high byte to TX_BASE_ADR + 1, as these form the first 2 bytes of the transmit packet. On issuing CMD_PHY_TX_15d4, the contents of these 2 bytes are copied into BB_PHR_LOW (Address 0x132) and BB_PHR_HIGH (Address 0x133), respectively. Likewise, on successful packet reception, the packet header bytes are copied into BB_PHR_LOW and BB_PHR_HIGH.

The following sections detail the PHR bit definitions: mode switch, reserved, FCS, whitening, and length.

Mode Switch

Bit 7 of the BB_PHR_LOW register is the MODE_SWITCH bit. The MODE_SWITCH bit is set to 0, indicating that there is no data rate or modulation scheme change during the packet transmission.

If the ADF7023-J receives a packet with mode switch, the MODE_SWITCH bit set to 1, it does not generate a PHR interrupt; however, it does generate an INTERRUPT_CRC_CORRECT interrupt and INTERRUPT_RX_EOF interrupt (if they are enabled).

If the ADF7023-J transmits a packet with MODE_SWITCH set to 1, the transmission is terminated after PHR and the PSDU is not transmitted.

Reserved

Bits[6:5] of the BB_PHR_LOW register are reserved. They are set to 0 for ADF7023-J firmware for transmit mode, and are ignored by the ADF7023-J firmware module in receive mode.

FCS

Bit 4 of the BB_PHR_LOW register is the FCS bit.

FCS = 0 indicates a 32-bit FCS. This case is not handled automatically by the ADF7023-J firmware download module. For transmit, the user must calculate the 32-bit CRC and add it to the PSDU. In receive mode, the 32-bit CRC is received as part of the PSDU and stored in the packet RAM, CRC is not validated, and the CRC interrupt is not asserted. The INTERRUPT_RX_EOF interrupt indicates when the packet is received.

FCS = 1 indicates a 16-bit CRC. This case is handled automatically by the firmware. In transmit mode, the 16-bit CRC is calculated and appended to the transmit PSDU. In receive mode, the 16-bit CRC is calculated from the incoming payload and, if the CRC is correct, the CRC interrupt is asserted (if enabled).

Whitening

Bit 3 of the BB_PHR_LOW register is the whitening bit. If the whitening bit = 0, the PSDU is not whitened; if the whitening bit = 1, the PSDU is whitened on transmission. Only the PSDU is whitened, not the SFD or PHR.

In receive mode, if the whitening bit is set to 1 in the received packet header, the ADF7023-J firmware download module automatically de-whitens the received PSDU.

Length

Bits[2:0] of the BB_PHR_LOW register define Bits[10:8] of the PSDU_LENGTH[10:0] word, and Bits[7:0] of the BB_PHR_HIGH register define Bits[7:0] of the PSDU_LENGTH[10:0] word.

The PSDU_LENGTH[10:0] word can be set to values in the range of 3 to 2047.

Tx/Rx Rolling Data Buffer

In packet mode, when the ADF7023-J receives a packet, the data is stored in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence. This functionality is described in the ADF7023-J data sheet.

If the IEEE 802.15.4g firmware download module is used, it is possible to receive or transmit packets that are longer than the available packet RAM. This is accomplished via a rolling buffer. The registers applicable to the operation of the rolling buffer are given in Table 37.

The 0x20 to 0xFF packet RAM locations are available for packet data. Byte 0x00 to Bye 0x1F are allocated for use by the on-chip processor and must not be used for packet data.

Rolling Buffer in Transmit Mode

In transmit mode, the start of the rolling buffer in packet RAM is set by TX_BASE_ADR. The size of the buffer is set by BB_TX_BUFFER_SIZE. Take care that the buffer size does not exceed the available packet RAM. When the value in BB_TX_BUFFER_SIZE is added to the address in TX_BASE_ADR, 0x0FF must not be exceeded.

The user must set the value in BB_TX_BUFFER_SIGNAL so that an INTERRUPT_BUFFER_ALMOST_FULL interrupt is generated prior to transmission of all the data in the buffer. Typically, BB_TX_BUFFER_SIGNAL is set so that the interrupt is received when half the data in the buffer has been transmitted.

When an INTERRUPT_BUFFER_ALMOST_FULL is asserted, the host microprocessor should write new data to the locations from TX_BASE_ADR to TX_BASE_ADR + BB_TX_BUFFER_SIGNAL.

When the data in the last byte of the Tx buffer has been transmitted, the ADF7023-J continues transmitting starting with the data at the TX_BASE_ADR. If enabled, an INTERRUPT_BUFFER_FULL interrupt is asserted when the last byte in the buffer is transmitted.

When an INTERRUPT_BUFFER_FULL is asserted, the host microprocessor should write new data to the locations from TX_BASE_ADR + BB_TX_BUFFER_SIGNAL + 1 to TX_BASE_ADR + BB_TX_BUFFER_SIZE.

Transmission of data continues until Tx_EOF or the user issues CMD_PHY_ON_15d4.

Rolling Buffer in Receive Mode

In receive mode, the start of the rolling buffer in packet RAM is set by RX_BASE_ADR. The size of the buffer is set by BB_RX_BUFFER_SIZE. Take care that the buffer size does not exceed the available packet RAM. When the value in BB_RX_BUFFER_SIZE is added to the address in RX_BASE_ADR, 0x0FF must not be exceeded. If 16-bit FCS checking on the ADF7023-J is enabled, 0x0FD must not be exceeded.

The user must set the value in BB_RX_BUFFER_SIGNAL so that an INTERRUPT_BUFFER_ALMOST_FULL interrupt is asserted prior to the buffer being filled by received data. Typically BB_RX_BUFFER_SIGNAL is set so that the interrupt is asserted when half the buffer has been filled with received data.

When an INTERRUPT_BUFFER_ALMOST_FULL is asserted, the host microprocessor should read in the data in the locations from RX_BASE_ADR to RX_BASE_ADR + BB_RX_BUFFER_SIGNAL.

When the last byte of the Rx buffer has been filled, the ADF7023-J continues writing the received data starting at the RX_BASE_ADR. If enabled, an INTERRUPT_BUFFER_FULL interrupt is asserted when the buffer has been filled.

When an INTERRUPT_BUFFER_FULL is asserted, the host microprocessor should read in the data in the locations from RX_BASE_ADR + BB_RX_BUFFER_SIGNAL + 1 to RX_BASE_ADR + BB_RX_BUFFER_SIZE.

Reception of data continues until RX_EOF, a CRC correct interrupt, or the host microprocessor issues CMD_PHY_ON_15d4.

Note that if 16-bit CRC is enabled (16-bit FCS), the FCS bytes are placed into the packet RAM as 2 bytes after the payload, outside of the rolling buffer control. Therefore, if the payload fills right up to RX_BASE_ADR + BB_RX_BUFFER_SIZE, when the 16-bitFCS is calculated and checked versus the incoming FCS, the received FCS bytes are placed in the next two memory locations (that is, beyond the RX_BASE_ADR + BB_RX_BUFFER_SIZE).

If another buffer is defined to start in the memory location immediately following an RX_BASE_ADR + BB_RX_BUFFER_SIZE, the first 2 bytes are overwritten.

To avoid this situation arising for any length and buffer size, an overflow area of 2 bytes must be left vacant immediately after the Rx buffer. If the Rx buffer is assigned the upper part of the packet memory, it must be set so as not to exceed the 0xFD memory location.

If the Rx buffer is placed lower down in packet memory and is immediately followed in packet memory by a Tx buffer, the TX_BASE_ADR must be set to be 3 bytes greater than RX_BASE_ADR + BB_RX_BUFFER_SIZE. This ensures that if the payload length places the packet end at the BB_RX_BUFFER_SIZE boundary, the overflow of the FCS byte(s) does not cause overwriting of the first 2 bytes of the following Tx buffer (the FCS bytes are written into the overflow bytes instead).

This overwriting issue does not arise in 32-bit CRC mode. In 32-bit CRC mode, the ADF7023-J does not calculate the CRC itself; therefore, the incoming 4 bytes of FCS are considered the same as the payload and are loaded into the receive buffer under rolling buffer control.

Recommended Register Settings

Recommended AGC Settings

To optimize the receiver for robust packet error rate performance over the full input power range, it is recommended to overwrite the default AGC clock divide setting in the MCR memory. The recommended setting is AGC_CLOCK_DIVIDE (Address 0x32F) = 0x12.

Tx LookUp Table (LUT) Settings

The optimized PLL bandwidth settings for T108 operation are built into the firmware download. Set Bits[5:4] of the RADIO_CFG_7 register (Address 0x113) to 0 when using the PHY_TX_15d4 state.

Reused BBRAM Settings

The ADF7023-J 15d4g firmware download reuses BBRAM registers, and therefore, some default functions are no longer available when in 15d4g mode.

Address matching or static register fix are not available with 15d4g download, because the BBRAM Register 0x129 to Register 0x137 are reused by the firmware to control the CCA functionality and 15d4g functionality.

Transmit test modes are not available within PHY_TX_15d4g. To use the transmit test modes, it is necessary to revert to PHY_ON to get to PHY_TX.

To use the optimized PLL settings for T108 operation in PHY_TX, the sequence outlined in the ADF7023-J data sheet must be followed.

Therefore, the full sequence from PHY_ON_15d4 to transmit test mode with optimized T108 PLL settings is as follows:

1. Issue B1 (exit 15d4g mode).
2. Use custom transmit LUT: write 0x2 to Bits[5:4] of Register 0x113 (RADIO_CFG_7).
3. Issue CMD_CONFIG_DEV.
4. Write the custom LUT as defined in Table 38.
5. Select the transmit test mode desired (see Table 42 in the ADF7023-J data sheet).
6. Enter PHY_TX.

Example Receiver Settings For 100 kbps and 200 kbps Operation, AFC Enabled

Specifications

Test Conditions

Code Download Sequence

The 15d4g firmware module must be stored in the PRAM starting from Address 0x0000.

The program RAM can be written to only by using the memory block write. SPI_MEM_WR must be set to 0x1E.

The sequence to write a firmware module to program RAM is as follows:

1. Ensure that the ADF7023-J is in PHY_OFF.
2. Issue the CMD_RAM_LOAD_INIT command.
3. Write the module to program RAM using an SPI memory block write.
4. Issue the CMD_RAM_LOAD_DONE command.

The firmware module is now stored in program RAM.

The program RAM is volatile memory and must be reloaded each time the transceiver wakes up from sleep state.

Author

Liam O'Hora