MAXQ1850
PRODUCTIONDeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography
Low Pin-Count Cryptographic Microcontroller with Advanced Physical Security
- Part Models
- 4
- 1ku List Price
- price unavailable
Part Details
- High-Performance 32-Bit MAXQ30 RISC Core
- DC to 16MHz Operation, Approaching 1MIPS per MHz
- Single 3.3V Supply Enables Low Power/Flexible Interfacing
- 65MHz Cryptography Engine Execution to Reduce Processing Time
- On-Chip 2x/4x Clock Multiplier
- 5V Tolerant I/O
- Up to 16 General-Purpose I/O Pins
- 33 Instructions, Most Single Cycle
- Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement
- Virtually Unlimited Software Stack
- 16-Bit Instruction Word, 32-Bit Internal Data Bus
- 16 x 32-Bit Accumulators
- CRC-16, CRC-32 generator
- Security Features
- Tamper Sensors Instantaneously "Zeroize" Internal Keys and User Data When:
- Out-of-Range Temperature/Voltage Detected
- User-Defined Self-Destruct Inputs (SDIx) Activated
- Internal Cryptographic Hardware Includes:
- DES Engine Supporting Single DES and 2/3-Key 3DES Operations
- AES Engine supporting 128-, 192- and 256-bit Key Length
- Public-Key Cryptographic Accelerator for ECDSA (160-, 192-, and 256-Key Strength)
- Public-Key Cryptographic Accelerator for DSA and RSA (1024- and 2048-Key Strength)
- Hardware Hash Engine Supports SHA-1, SHA-224, SHA-256
- Unresettable True-Time Clock Self-Imposes Expiration Dates and Date/Timestamping
- Tamper Sensors Instantaneously "Zeroize" Internal Keys and User Data When:
- Memory Features
- Secure Memory Management Unit
- 256KB of Internal Flash Program Memory
- 8KB Internal Battery-Backed NV SRAM
- Peripheral Features
- USB Device Controller with Four Endpoint Buffers
- ISO 7816 UART with FIFO with Two Physically Separate Communication Buses
- One General Purpose UART
- Two 16-bit Timers
- Power Management Features
- In-System Programming Through Debug Port or Serial Port
- Ultra-Low Battery Leakage to Support NV RAM and Security Sensors (130nA)
Physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with rapid zeroization of critical data. Four self-destruct inputs are provided for additional tamper response. An internal shield over the silicon provides protection from microprobe attacks. A high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. To protect data, the MAXQ1850 integrates several high-speed, analysis-resistant encryption engines. Algorithms supported in hardware include AES (128-, 192-, and 256-bit), DES, triple DES (2-key and 3-key), ECDSA (160-, 192-, and 256-bit keys), DSA, RSA (up to 2048 bits), SHA-1, SHA-224, and SHA-256. The advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria certifications.
The MAXQ1850 includes 256KB of flash memory and 8KB of secure, battery-backed data SRAM. Several communication protocols are supported with hardware engines, including ISO 7816 for smart card applications, USB (slave interface with four end-point buffers), an RS-232 universal synchronous/asynchronous receiver-transmitter (USART), an SPI interface (master or slave mode support), and up to 16 general-purpose I/O pins. Other peripherals supported on the MAXQ1850 include a true hardware random-number generator (RNG), a real-time clock (RTC), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (PWM) operations.
Note: Designers must have following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation.
- MAXQ1850 IC data sheet
- MAXQ1850 revision-specific errata sheet (Click here for availability)
- MAXQ® Family User's Guide
- MAXQ Family User's Guide: MAXQ1850 Supplement (contact BU for availability)
Applications
- ATM Keyboards
- Certificate Authentication
- Electronic Commerce
- Electronic Signature Generator
- EMV® Banking
- Pay-per-Play
- PCI Terminals
- PIN Pads
- Secure Access Control
- Secure Data Storage
Documentation
Data Sheet 1
Reliability Data 1
User Guide 3
Application Note 1
Design Note 1
Technical Articles 1
Request an NDA
Complete documentation is available upon completion of a Non-Disclosure Agreement (NDA).
Request an NDAADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| MAXQ1850-BNS+ | 40-LFCSP-6X6X0.75 | ||
| MAXQ1850-BNS+T | 40-LFCSP-6X6X0.75 | ||
| MAXQ1850-DNS+ | 0-CHIP-N/A | ||
| MAXQ1850-LNS+ | Chip-Scale Ball-Grid Array |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
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