MAX9160
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
Part Details
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and ±100ps maximum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V supply voltage over the extended temperature range of -40°C to +85°C. This device is available in 28-pin exposed- and nonexposed-pad TSSOP and 32-lead 5mm x 5mm QFN packages.
Applications
- Add/Drop Multiplexers
- Cell Phone Base Stations
- Digital Cross-Connects
- DSLAM
- Network Equipment
- Servers
Documentation
Data Sheet 1
Reliability Data 1
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Level Translators 2 | ||
| MAX9311 | PRODUCTION | 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers |
| MAX9312 | PRODUCTION | Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers |
| Product 2 | ||
| MAX9313 | 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers | |
| MAX9314 | Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers | |
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