MAX5868
NOT RECOMMENDED FOR NEW DESIGNS16-Bit, 5Gsps Interpolating and Modulating RF DAC
Direct RF Synthesis of 500MHz Instantaneous Bandwidth from DC to Greater than 2GHz
- Part Models
- 1
- 1ku List Price
- Starting From $108.07
Part Details
- Direct RF Synthesis Solution for Communications
- 4.96Gsps DAC Output Update Rate
- High-Performance 14-Bit RF DAC Core
- Digital Quadrature Modulator and NCO with 1Hz/10Hz/100Hz/1kHz/10kHz Resolution
- 4x/5x/6x/8x/10x/12x/16x/20x/24x Interpolation
- 16-Bit 1240Mwps DDR Parallel LVDS Data Bus
- Highly Flexible and Configurable
- Data Bus with Word, Byte and Nibble Modes
- Reference Clock Output for FPGA Interface
- Multiple DAC Synchronization
- SPI Interface for Device Configuration
- Low Power, Compact Solution
- 1.5W at fCLK = 5Gsps
- 10mm x 10mm, 144-Pin CSBGA
The MAX5868 high-performance interpolating and modulating 16-bit 5Gsps RF DAC can directly synthesize up to 500MHz of instantaneous bandwidth from DC to frequencies greater than 2GHz. The device is optimized for cable and digital video broadcast applications and meets spectral mask requirements for a broad set of communication standards including EPoC, DVB-T, DVB-T2, DVB-C2, ISDB-T, and DOCSIS 3.0/3.1.
The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO) and a 14-bit RF DAC core. The user-configurable 4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x or 24x, linear phase interpolation filters reduce the input data bandwidth required from an FPGA/ASIC. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis.
The MAX5868 includes a source synchronous 16-bit parallel LVDS data input interface. The input baseband I and Q signals are time interleaved on a single parallel input port configured for double data rate clocking at up to 1240Gwps (620Mwps I and Q each). The device accepts data in word (16 bit), byte (8 bit), or nibble (4 bit) modes. The input data is aligned to the data clock supplied with the data. An input FIFO decouples the timing of the input interface from the DAC update clock domain. In addition, a parity input and parity flag interrupt output are available to ensure data integrity.
The MAX5868 clock input has a flexible clock interface and accepts a differential sine-wave or square-wave input clock signal. The device outputs a divided reference clock to ensure synchronization with the FPGA/ASIC driving its input port. In addition, dedicated input and output signals are provided for synchronizing multiple devices.
The MAX5868 uses a differential current-steering architecture and can produce a 0dBm full-scale output signal level with a 50Ω load. Operating from 1.8V and 1.0V power supplies, the device consumes 1.5W at 5Gsps. The device is offered in a compact 144-pin CSBGA package and is specified for the extended temperature range (-40°C to +85°C).
Applications
- Digital Video Broadcast
- Downstream DOCSIS CMTS Modulators
- DVB-T/DVB-T2/DVB-C2/ISDB-T Modulators
- Ethernet PON over Coax (EPoC)
Documentation
Data Sheet 1
Technical Articles 6
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| MAX5868EXE+ | Chip-Scale Ball-Grid Array |
This is the most up-to-date revision of the Data Sheet.
Tools & Simulations
Software Development 1
IBIS Model 1
Evaluation Kits
Evaluation Kit for the MAX5868
Resources
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