DS3171

Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers

Data Sheet (Rev. 2)

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Part Details

Single (DS3171), Dual (DS3172), Triple (DS3173), or Quad (DS3174) Single-Chip Transceiver for DS3 and E3
All Four Devices are Pin Compatible for Ease of Port Density Migration in the Same Printed Circuit Board Platform
Each Port Independently Configurable
Performs Receive Clock/Data Recovery and Transmit Waveshaping for DS3 and E3
Jitter Attenuator can be Placed Either in the Receive or Transmit Paths
Interfaces to 75Ω Coaxial Cable at Lengths Up to 380 meters, or 1246 feet (DS3) or 440 meters, or 1443 feet (E3)
Uses 1:2 Transformers on Both Tx and Rx
On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer(s)
Ports Independently Configurable for DS3, E3
Built-In HDLC Controllers with 256-Byte FIFOs for the Insertion/Extraction of DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC Bytes
On-Chip BERTs for PRBS and Repetitive Pattern Generation, Detection, and Analysis
Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second
Flexible Overhead Insertion/Extraction Ports for DS3, E3 Framers
Loopbacks Include Line, Diagnostic, Framer, Payload, and Analog with Capabilities to Insert AIS in the Directions Away from Loopback Directions
Ports can be Disabled to Reduce Power
Integrated Clock Rate Adapter to Generate the Remaining Internally Required 44.736MHz (DS3) and 34.368MHz (E3) from a Single Clock Reference Source at One of Three Standard Frequencies (DS3, E3, STS-1)
Pin Compatible with the DS318x Family of Devices and the DS316x Family of Devices
8-/16-Bit Generic Microprocessor Interface
Low-Power (~1.73W) 3.3V Operation (5V Tolerant I/O)
Small High-Density Thermally Enhanced Chip- Scale BGA Packaging (TE-CSBGA) with 1.27mm Pin Pitch
Industrial Temperature Operation: -40°C to +85°C
IEEE1149.1 JTAG Test Port