DS21554

NOT RECOMMENDED FOR NEW DESIGNS

3.3V/5V E1 Single Chip Transceivers (SCT)

Data Sheet (Rev. 1)

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Part Details

Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality
On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Frames to FAS, CAS, CCS, and CRC4 Formats
Integral HDLC Controller with 64-Byte Buffers Configurable for Sa Bits, DS0, or Sub-DS0 Operation
Dual Two-Frame Elastic Store Slip Buffers that can Connect to Asynchronous Backplanes up to 8.192MHz
Interleaving PCM Bus Operation
8-Bit Parallel Control Port that can be used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola)
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS Alarms
Programmable Output Clocks for Fractional E1, H0, and H12 Applications
Fully Independent Transmit and Receive Functionality
Full Access to Si and Sa Bits Aligned with CRC-4 Multiframe
Four Separate Loopback Functions for Testing Functions
Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits
IEEE 1149.1 JTAG-Boundary Scan Architecture
Pin Compatible with DS2154/52/352/552 SCTs
3.3V (DS21354) or 5V (DS21554) Supply; Low- Power CMOS
100-pin LQFP package (14mm x 14mm)

Documentation

Data Sheet 1

DS21354-DS21554: 3.3V/5V E1 Single Chip Transceivers (SCT) Data Sheet (Rev.1) 02/10/2004
- DS21354-DS21554: Errata Sheet
- DS21354-DS21554: Errata Sheet
- DS21354-DS21554: Errata Sheet
- DS21354-DS21554: Errata Sheet

Reliability Data 1

DS21554 Reliability Data 01/12/2023

Application Note 4

T1/E1 Network Interface Design 11/27/2001

Using RCLK in a BITS/SSU Application 02/04/2002

DS2155 vs. DS21x5y: Software and Hardware Considerations 12/06/2001

DS21Q4x, DS215x, and DS21x5y Test Registers 03/29/2001

Design Note 18

Elastic Store Operation 06/28/2004

Telecom Application Notes Index 08/10/2001

Provision Your DS2152 or DS2154 Hardware Design for the Next Generation Devices 03/29/2001

T1/E1 Framer Initialization and Programming 08/10/2001

DS2153 Programming, ETS 300-011 Remote Alarm Generation 05/15/2001

DS2151, DS2153 Device Identification 10/15/2001

DS21354/DS21554 vs. DS2154 Single Chip Transceivers 08/10/2001

HDLC Configuration of Framers and Transceivers 09/10/2002

NRZ Applications 08/30/2002

DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide 06/20/2002

DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32) 08/13/2002

T1/E1 Loopback Operation for Maxim T1/E1/J1 Transceivers 11/04/2004

DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert 02/15/2002

Interfacing to the Fractional T1 and E1 05/04/2001

Conversion Between T1 and E1 12/26/2001

Interfacing the DS2155 to the MPC8260 02/04/2002

Power-Fault Protection Layout 06/06/2003

Interleaved Bus Operation 03/20/2006

Technical Articles 5

E1 Operation of Dallas Semiconductor Framers and SCTs 09/10/2002

Measuring Return Loss on T3/E3/STS-1 LIUs 06/20/2005

Selecting a T1/E1/J1 Single-Chip Transceiver 03/24/2004

Hitless Protection Switching with 1+1 Redundancy 06/07/2002

T1/E1 and T3/E3 Transformer Selection Guide 10/15/2001

This is the most up-to-date revision of the Data Sheet.

Tools & Simulations

BSDL Model File 1

ADSP-DS21554 BSDL Model

IBIS Model 1

DS21554 IBIS Model

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