ADL5308
RECOMMENDED FOR NEW DESIGNSFast Response 188 dB Range (10 pA to 25 mA) Logarithmic Converter
- Part Models
- 2
- 1ku List Price
- Starting From $9.82
Part Details
- Fast transient response (IPD stepped from 220 μA to 10 nA)
- Rise/fall time: <2.4 μs
- 2 dB Electrical (1 dB optical) settling time: <3.5 μs
- Flat Frequency Response/No Undershoot
- Bandwidth: 970 kHz at IINP = 10 nA
- Accurately trimmed logarithmic response
- Logarithmic slope: 200 mV/dec
- Logarithmic conformance error: ±0.2 dB at 25°C (IINP from 10 nA to 1 mA)
- Ratio input for direct optical gain measurements
- Comparator with adjustable hysteresis and latch enable
- Analog and digital comparator reference
- I2C adjustable
- Adaptive photodiode bias
- Comparator reference level
- Minimal external components are required
- 34 dB PSRR at 20 kHz and IINP = 10 nA
- 2 mm × 3 mm, 14-terminal LGA package
The ADL5308 is a logarithmic transimpedance amplifier optimized for wide dynamic range signal level monitoring in fiber optic systems.
It produces an accurate, temperature-compensated output voltage proportional to the logarithm of the ratio between the input current at pin INP, and a reference current. The reference current can either be generated internally or externally provided through the IREF interface (LOG-ratio detection). The logarithmic slope and intercept are both accurately trimmed to a nominal value of 200 mV/decade and 10 pA respectively.
The low-impedance VLOG logarithmic output has enough drive capability to drive a wide range of analog-to-digital converters (ADCs) and other circuits and its gain can be adjusted by adding a resistor-divider driving the FB pin.
A built-in fast comparator provides a compact solution to compare the logarithmic output to an external reference level, either programmed through I2C or supplied through the CREF interface. The comparator has adjustable hysteresis and an optional output latch function using the HYST pin.
Adaptive photodiode (PD) biasing is supported through the PDB pin. At a low diode current, the reverse PD bias is kept small to minimize the dark current. At higher input currents, the bias voltage scales linearly with the current to avoid nonlinearity due to PD saturation. The starting bias level as well as the scale factor at higher currents are configurable through I2C.
The ADL5308 is specified for operation from −40°C to +105°C ambient temperature and is offered in a small 2 mm × 3 mm, 14-terminal LGA package.
Applications
Documentation
Data Sheet 1
User Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADL5308ACCZ | 14-Lead LGA (2mm x 3mm x 0.676 mm) | ||
| ADL5308ACCZ-R7 | 14-Lead LGA (2mm x 3mm x 0.676 mm) |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| LDO Plus 1 | ||
| LT3042 | RECOMMENDED FOR NEW DESIGNS | 20V, 200mA, Ultralow Noise, Ultrahigh PSRR RF Linear Regulator |
| Positive Linear Regulators (LDO) 2 | ||
| ADP7118 | RECOMMENDED FOR NEW DESIGNS | 20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator |
| ADP7112 | RECOMMENDED FOR NEW DESIGNS | 20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator |
Evaluation Kits
Evaluating the ADL5308 Fast Response 188 dB Range (10 pA to 25 mA) Logarithmic Converter